1. A chip-size double side connection package configured such that a semiconductor chip including a semiconductor substrate on which an LSI region and electrode connection regions are formed is connected to wiring for external connection provided on a first main face and to wiring for external connection provided on a second main face, the first and second main faces being located above and below the semiconductor chip, respectively, the chip-size double side connection package comprising:
a low resistance metal charged into holes formed in the electrode connection regions to form through electrodes;
a wiring-added post electrode component which includes post electrodes and front face wiring traces connected to the post electrodes fixed to and electrically connected to upper surface regions of the through electrodes or the electrode connection regions;
a resin between the semiconductor chip and the front face wiring traces; and
tip ends on the second main face of the through electrodes configured for use as the wiring for external connection.
2. The chip-size double side connection package according to claim 1, wherein external electrodes for external connection are formed on the front face wiring traces so as to be connected thereto.
3. (canceled)
4. The chip-size double side connection package according to claim 1, wherein, on the second main face side, a back face insulation layer is applied to the semiconductor substrate such that the tip ends of the through electrodes are exposed, and back face wiring traces to be connected to the tip ends of the through electrodes are formed.
5. The chip-size double side connection package according to claim 4, wherein, on the second main face side, external electrodes to be connected to the back face wiring traces are formed.
6. The chip-size double side connection package according to claim 1, wherein, after the holes corresponding to the through electrodes are formed in the semiconductor substrate, an insulation film is deposited on the wall surfaces of the holes.
7-9. (canceled)
10. A method for manufacturing a chip-size double side connection package configured such that a semiconductor chip including a semiconductor substrate on which an LSI region and electrode connection regions are formed is connected to wiring for external connection provided on a first main face and to wiring for external connection provided on a second main face, the first and second main faces being located above and below the semiconductor chip, respectively, the method being characterized by comprising:
forming a wiring-added post electrode component which includes post electrodes supported by a support portion and front face wiring traces connected to the post electrodes;
forming holes corresponding to through electrodes in the semiconductor substrate at or in the vicinity of the centers of the electrode connection regions to which the through electrodes are to be connected;
charging a low resistance metal into the holes to thereby form the through electrodes;
simultaneously fixing and electrically connecting the plurality of post electrodes of the wiring-added post electrode component, which are coupled together by the support portion, to upper surface regions of the through electrodes or the electrode connection regions;
on the first main face side, charging resin into a space between the semiconductor chip and the support portion, and then separating the support portion so as to expose the front face wiring traces; and
on the second main face side, grinding the semiconductor substrate to form a ground semiconductor substrate so as to expose tip ends of the through electrodes,
wherein the front face wiring traces exposed to the first main face side and the tip ends of the through electrodes exposed to the second main face side are used as the wiring for external connection.
11. The method for manufacturing the chip-size double side connection package according to claim 10, wherein external electrodes for external connection are formed on the front face wiring traces so as to be connected thereto.
12. The method for manufacturing the chip-size double side connection package according to claim 10, wherein, on the second main face side, a back face insulation layer is applied to the ground semiconductor substrate such that the tip ends of the through electrodes are exposed, and external electrodes to be connected to the tip ends of the through electrodes are formed.
13. The method for manufacturing the chip-size double side connection package according to claim 10, wherein, on the second main face side, a back face insulation layer is applied to the ground semiconductor substrate such that the tip ends of the through electrodes are exposed, and back face wiring traces to be connected to the tip ends of the through electrodes are formed.
14. The method for manufacturing the chip-size double side connection package according to claim 13, wherein, on the second main face side, external electrodes to be connected to the back face wiring traces are formed.
15. The method for manufacturing the chip-size double side connection package according to claim 10, wherein, after the holes corresponding to the through electrodes are formed in the semiconductor substrate, an insulation film is deposited on the wall surfaces of the holes.
16. The method for manufacturing the chip-size double side connection package according to claim 10, wherein the wiring-added post electrode component is fabricated such that columnar post electrodes with wiring are grown on an electrically conductive material, which serves as the support portion, to thereby form wiring-added post electrodes integrated with the support portion.
17. The method for manufacturing the chip-size double side connection package according to claim 10, wherein the wiring-added post electrode component is fabricated such that columnar post electrodes with wiring are grown on an insulation tape of thin film applied to one entire surface of the support portion, to thereby form wiring-added post electrodes integrated with the support portion.
18. The method for manufacturing the chip-size double side connection package according to claim 17, wherein, on the first main face side, the insulation tape left after separation of the support portion is used as a protection film.
19. (canceled)
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A capacitive sensor array, comprising:
a plurality of large sensor electrodes located within an active sensing region;
a plurality of small sensor electrodes including a first set of at least four small sensor electrodes and a second set of at least four small sensor electrodes located within the active sensing region, wherein the plurality of large sensor electrodes and the plurality of small sensor electrodes are formed from a single layer of conductive material; and
a plurality of pads located within an edge region bordering the active sensing region,
wherein each small sensor electrode of the first set of small sensor electrodes is electrically connected by a first conductive path through a first set of connecting traces to a first pad of the plurality of pads, wherein a first axis crosses two or more of the small sensor electrodes of the first set of small sensor electrodes, wherein each small sensor electrode of the first set of small sensor electrodes is located on an opposite lateral side of one of the plurality of large sensor electrodes from another small sensor electrode of the first set of small sensor electrodes,
wherein each small sensor electrode of the second set of small sensor electrodes is electrically connected by a conductive path through a second set of connecting traces to a second pad of the plurality of pads, wherein the first conductive path is non-overlapping with the second conductive path, wherein a second axis crosses two or more of the small sensor electrodes of the second set of small sensor electrodes, wherein each small sensor electrode of the second set of small sensor electrodes is located on an opposite lateral side of one of the plurality of large sensor electrodes from another small sensor electrode of the second set of small sensor electrodes.
2. The capacitive sensor array of claim 1, wherein a conductive path through the first set of connecting traces and the first set of small sensor electrodes passes through the edge region and a routing region bordering the active sensing region on an opposite side of the active sensing region from the edge region.
3. The capacitive sensor array of claim 1, wherein for each small sensor electrode of the plurality of sensor electrodes, a shortest line segment between a geometric center of the small sensor electrode and a central longitudinal axis of a large sensor electrode nearest to the geometric center crosses a ground trace and does not cross any other small electrode.
4. The capacitive sensor array of claim 1, wherein the first pad is connected at opposite ends of the first pad to two connecting traces of the first set of connecting traces, and wherein the second pad is connected at opposite ends of the second pad to two connecting traces of the second set of connecting traces.
5. The capacitive sensor array of claim 1, wherein the plurality of pads comprises a pad for each large sensor electrode of the plurality of large sensor electrodes and for each of a plurality of sets of small sensor electrodes, wherein each small sensor electrode in the plurality of sets of small sensor electrodes is electrically connected to every other small sensor electrode in the same set of small sensor electrodes by a set of connecting traces, and wherein the plurality of sets of small sensor electrodes comprises the first set of sensor electrodes and the second set of sensor electrodes.
6. The capacitive sensor array of claim 5, further comprising one or more ground traces in the active sensing region, wherein a number of pads in the edge region is less than or equal to one pad for each large sensor electrode of the plurality of sensor electrodes, for each set of small sensor electrodes of the plurality of small sensor electrodes, and for each of the one or more ground traces.
7. The capacitive sensor array of claim 1, wherein a third axis perpendicular to the first axis and the second axis crosses at least one of the first set of small sensor electrodes and at least one of the second set of small sensor electrodes.
8. The capacitive sensor array of claim 7, wherein a fourth axis parallel to the third axis crosses two or more of the plurality of large sensor electrodes.
9. The capacitive sensor array of claim 8, further comprising one or more additional sets of small sensor electrodes, wherein each small sensor electrode in the one or more additional sets of small sensor electrodes is electrically coupled to every other small sensor electrode in the same set of small sensor electrodes by a set of connecting traces, wherein for each of the two or more large sensor electrodes crossed by the fourth axis, the third axis crosses one small sensor electrode from each of the additional sets of small sensor electrodes.
10. A capacitive sensor array, comprising:
a plurality of large sensor electrodes located within an active sensing region;
a plurality of small sensor electrodes including a first set of small sensor electrodes and a second set of small sensor electrodes located within the active sensing region, wherein the plurality of large sensor electrodes and the plurality of small sensor electrodes are formed from a single layer of conductive material; and
a plurality of pads located within an edge region bordering the active sensing region,
wherein a first conductive path through each of the first set of small electrodes extends from a first pad of the plurality of pads to a routing region opposite the edge region and extends from the routing region to the edge region, wherein a first axis crosses two or more of the small sensor electrodes of the first set of small sensor electrodes, wherein each small sensor electrode of the first set of small sensor electrodes is located on an opposite lateral side of one of the plurality of large sensor electrodes from another small sensor electrode of the first set of small sensor electrodes,
wherein a second conductive path through each of the second set of small electrodes is non-overlapping with the first conductive path and extends from a second pad of the plurality of pads to a routing region opposite the edge region and extends from the routing region to the edge region, wherein a second axis crosses two or more of the small sensor electrodes of the second set of small sensor electrodes, wherein each small sensor electrode of the second set of small sensor electrodes is located on an opposite lateral side of one of the plurality of large sensor electrodes from another small sensor electrode of the second set of small sensor electrodes.
11. The capacitive sensor array of claim 10, wherein for each small sensor electrode of the plurality of sensor electrodes, a shortest line segment between a geometric center of the small sensor electrode and a central longitudinal axis of a large sensor electrode nearest to the geometric center crosses a ground trace and does not cross any other small electrode.
12. The capacitive sensor array of claim 10, wherein the first pad is connected at opposite ends of the first pad to two connecting traces of the first set of connecting traces, and wherein the second pad is connected at opposite ends of the second pad to two connecting traces of the second set of connecting traces.
13. The capacitive sensor array of claim 10, wherein the plurality of pads comprises a pad for each large sensor electrode of the plurality of large sensor electrodes and for each of a plurality of sets of small sensor electrodes, wherein each small sensor electrode in the plurality of sets of small sensor electrodes is electrically connected to every other small sensor electrode in the same set of small sensor electrodes by a set of connecting traces, and wherein the plurality of sets of small sensor electrodes comprises the first set of sensor electrodes and the second set of sensor electrodes.
14. The capacitive sensor array of claim 10, further comprising a plurality of sets of small sensor electrodes, wherein the plurality of sets of small sensor electrodes comprises the first set of small sensor electrodes and the second set of small sensor electrodes, wherein each small sensor electrode in the plurality of sets of small sensor electrodes is electrically coupled to every other small sensor electrode in the same set of small sensor electrodes by a set of connecting traces, wherein a third axis perpendicular to the first axis and the second axis crosses two or more of the plurality of large sensor electrodes, wherein for each of the two or more large sensor electrodes crossed by the third axis, a fourth axis parallel to the third axis crosses one small sensor electrode from each of the plurality of sets of small sensor electrodes.
15. A method, comprising:
providing a plurality of large sensor electrodes located within an active sensing region;
providing a plurality of small sensor electrodes including a first set of at least four small sensor electrodes and a second set of at least four small sensor electrodes located within the active sensing region, wherein the plurality of large sensor electrodes and the plurality of small sensor electrodes are formed from a single layer of conductive material; and
providing a plurality of pads coupled with the capacitance sensor and located within an edge region bordering the active sensing region;
wherein each small sensor electrode of the first set of small sensor electrodes is electrically connected by a first conductive path through a first set of connecting traces to a first pad of the plurality of pads, wherein a first axis crosses two or more of the small sensor electrodes of the first set of small sensor electrodes, wherein each small sensor electrode of the first set of small sensor electrodes is located on an opposite lateral side of one of the plurality of large sensor electrodes from another small sensor electrode of the first set of small sensor electrodes,
wherein each small sensor electrode of the second set of small sensor electrodes is electrically connected by a second conductive path through a second set of connecting traces to a second pad of the plurality of pads, wherein the first set of conductive paths is non-overlapping with the second set of conductive paths, wherein a second axis crosses two or more of the small sensor electrodes of the second set of small sensor electrodes, wherein each small sensor electrode of the second set of small sensor electrodes is located on an opposite lateral side of one of the plurality of large sensor electrodes from another small sensor electrode of the second set of small sensor electrodes.
16. The method of claim 15, wherein a first conductive path through the first set of connecting traces and the first set of small sensor electrodes passes through the edge region and a routing region bordering the active sensing region opposite the edge region, and wherein a second conductive path through the second set of connecting traces and the second set of small sensor electrodes passes through the edge region and the routing region.
17. The method of claim 15, further comprising providing one or more ground traces in the active sensing region, wherein a number of the plurality of pads in the edge region is less than or equal to one pad for each large sensor electrode of the plurality of sensor electrodes, for each set of electrically connected small sensor electrodes of the plurality of small sensor electrodes, and for each of the one or more ground traces.
18. The method of claim 15, wherein the plurality of pads comprises a pad for each large sensor electrode of the plurality of large sensor electrodes and for each of a plurality of sets of small sensor electrodes, wherein each small sensor electrode in the plurality of sets of small sensor electrodes is electrically coupled to every other small sensor electrode in the same set of small sensor electrodes by a set of connecting traces, wherein the plurality of sets of small sensor electrodes comprises the first set of sensor electrodes and the second set of sensor electrodes.
19. The capacitive sensor array of claim 15, wherein for each small sensor electrode of the plurality of sensor electrodes, a shortest line segment between a geometric center of the small sensor electrode and a central longitudinal axis of a large sensor electrode nearest to the geometric center crosses a ground trace and does not cross any other small electrode, and wherein the first pad is connected at opposite ends of the first pad to two connecting traces of the first set of connecting traces, and wherein the second pad is connected at opposite ends of the second pad to two connecting traces of the second set of connecting traces.
20. The capacitive sensor array of claim 15, wherein a third axis perpendicular to the first axis and the second axis crosses at least one of the first set of small sensor electrodes and at least one of the second set of small sensor electrodes, and wherein a fourth axis parallel to the third axis crosses two or more of the plurality of large sensor electrodes.