1. Electronically controllable brake actuating system for automotive vehicles, comprising:
means for measuring fluid pressure exerted by a pressure fluid,
means for measuring volume change of the pressure fluid,
a hydraulic arrangement including a piston-and-cylinder unit responsive to a pressure fluid pressure at an input thereto and in response to the pressure fluid pressure displaces a defined volume of pressure fluid and is interposed between a pressure source and an associated wheel brake and includes a pressure sensor arranged for sensing a pressure rise which is associated with the displaced volume of pressure fluid.
2. Electronically controllable brake actuating system as claimed in claim 1, wherein a valve assembly is provided in a first line that leads from the pressure source to the piston-and-cylinder unit and permits closing of the first line.
3. Electronically controllable brake actuating system as claimed in claim 2, further including a second line interposed between the valve assembly and the piston-and-cylinder unit wherein said second line communicates with a pressure fluid supply reservoir and a restrictor.
4. Device for detecting the presence of compressible fluid mixed with non-compressible fluid in the brake system of a vehicle, comprising:
a piston-and-cylinder unit interposed between a pressure source and an associated wheel brake, wherein said piston-and-cylinder unit is responsive to a pressure fluid pressure at an input thereto and in response to the pressure fluid pressure detects gases or air disposed in the system, by permitting the application of a defined pressure fluid volume to at least one wheel brake,
a pressure sensor arranged for sensing the pressure rise which is caused in the wheel brake by the effect of the pressure fluid volume, and
a valve assembly is provided in a line that leads from the pressure source to the piston-and-cylinder unit and permits closing of the line.
5. Electronically controllable brake actuating system for automotive vehicles, comprising:
a pressure source;
a valve assembly is provided in a first line that leads from the pressure source to a piston-and-cylinder unit wherein the piston is responsive to a pressure fluid pressure at an input to the piston-and-cylinder unit for determining hydraulic pressure to at least one wheel brake and wherein the valve assembly permits closing of the first line;
a pressure fluid supply reservoir in communication with a second line interposed between the valve assembly and the piston-and-cylinder unit;
wherein an amount of gases in the system is determined from a volume-pressure characteristic curve.
6. Electronically controllable brake actuating system as claimed in claim 5, further comprising a travel sensor for sensing an amount of travel of the piston.
7. Electronically controllable brake actuating system as claimed in claim 5, wherein said pressure fluid supply reservoir comprises a piston-type accumulator arranged in a reservoir filled with pressure fluid.
8. Electronically controllable brake actuating system as claimed in claim 7, wherein said piston-type accumulator includes supply bores that open into an unpressurized chamber contained in a sealed housing for preventing propagation of unwanted gases into the system.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An analog standard cell library comprising at least one analog standard cell family, said family:
defines an analog circuit function or portion thereof;
defines at least one variable analog circuit parameter of said analog circuit function; and
comprises a plurality of analog standard cells; wherein
each said analog standard cell:
comprises a physical design layout of said analog circuit function;
defines a cell height; and
defines a variation of said circuit parameter; wherein
all said analog standard cells:
have equal said cell height;
have different said physical design layout of said analog circuit function; and
have different said variation of said circuit parameter.
2. A general type analog standard cell whose generally planar layout defines a cell height and comprises:
a plurality of parallel and separated n-type poly fingers;
a plurality of parallel and separated p-type poly fingers;
an n-type diffusion adjacent to said n-type poly fingers;
a p-type diffusion adjacent to said p-type poly fingers; and
a plurality of conductive segments, wherein
said n-type poly fingers extend in both planar vertical directions beyond said n-type diffusion and said p-type poly fingers extend in both planar vertical directions beyond said p-type diffusion;
said n-type diffusion extends in both planar horizontal directions beyond said n-type poly fingers, and said p-type diffusion extends in both planar horizontal directions beyond said p-type poly fingers;
a first conductive segment is coupled to a first group of zero or more adjacent said n-type fingers;
a second conductive segment is coupled to a second group of said n-type fingers comprising all said n-type fingers not included in said first group;
a third conductive segment is coupled to a third group of zero or more adjacent said p-type fingers;
a fourth conductive segment is coupled to a fourth group of said p-type fingers comprising all p-type fingers not included in said third group;
fifth and sixth conductive segments are coupled to said n-type diffusion at locations adjacent to and only on opposite sides of each said n-type finger of said first group;
seventh and eighth conductive segments are coupled to said p-type diffusion at locations adjacent to and only on opposite sides of each said p-type finger of said third group;
a ninth conductive segment is coupled to said n-type diffusion at locations adjacent to each said n-type finger of said second group and not already coupled to either of said fifth or sixth conductive segments; and
a tenth conductive segment is coupled to said p-type diffusion at locations adjacent to each said p-type finger of said fourth group and not already coupled to either of said seventh or eighth conductive segments.
3. A sourcedrain-shared type analog standard cell whose generally planar layout defines a cell height and comprises:
a plurality of parallel and separated poly fingers;
a diffusion adjacent to said poly fingers;
a plurality of conductive segments, wherein
said poly fingers are all of the same doping type as each other and of the same doping type as said diffusion, said doping type either n-type or p-type;
said poly fingers extend in both planar vertical directions beyond said diffusion;
said diffusion extends in both planar horizontal directions beyond said poly fingers;
a first conductive segment is coupled to a first group of zero or more pairs of adjacent said fingers;
a second conductive segment is coupled to a second group of zero or more pairs of adjacent said fingers not included in said first group;
a third conductive segment is coupled to a third group of said fingers comprising all said fingers not included in said first and said second groups;
a fourth conductive segment is coupled to said diffusion at locations adjacent to and only on opposite sides of each said pair of fingers of said first group;
a fifth conductive segment is coupled to said diffusion at locations adjacent to and only between each said finger of each said pair of fingers of said first group;
a sixth conductive segment is coupled to said diffusion at locations adjacent to and only on opposite sides of each said pair of fingers of said second group; and
a seventh conductive segment is coupled to said diffusion at locations adjacent to and only between each said finger of each said pair of fingers of said second group;
4. An SoC physical design flow including at least one standard cell library of claim 1 and defining one or more layout rows, wherein
said layout rows each have a specified row height;
said standard cell library includes one or more analog standard cells and zero or more digital standard cells;
each said analog standard cell has cell height equal to one of said row heights or to an integer multiple thereof; and
each said digital standard cell has cell height equal to one of said row heights or to an integer multiple thereof; wherein
said SoC physical design flow can accept as input an SoC design description comprising either or both analog circuits and digital circuits; and
said SoC physical design flow performs the following tasks:
maps one or more said analog circuits, or portions thereof, to at least one of said analog standard cells andor said digital standard cells, and maps one or more said digital circuits, or portions thereof, to at least one of said digital standard cells andor said analog standard cells, said mapping occurring concurrently, serially, or in parallel;
places each said mapped analog standard cell, and places said said mapped digital standard cell, within a said layout row that has said row height equal to said cell height or across an integer number of adjacent said layout rows that has total height equal to said cell height, said placement occurring concurrently, serially, or in parallel; and
routes interconnect lines to and from said mapped analog standard cells, and routes interconnect lines to and from said mapped digital standard cells, said routing occurring concurrently, serially, or in parallel.
5. An SoC physical design flow including at least one standard cell library and defining one or more layout rows, wherein
said layout rows each have a specified row height;
said standard cell library includes at least one general type analog standard cell of claim 2 and zero or more digital standard cells;
each said general type analog standard cell has cell height equal to one of said row heights or to an integer multiple thereof; and
each said digital standard cell has cell height equal to one of said row heights or to an integer multiple thereof; wherein said SoC physical design flow can accept as input an SoC design description comprising either or both analog circuits and digital circuits; and
said SoC physical design flow performs the following tasks:
maps one or more said analog circuits, or portions thereof, to at least one of said general type analog standard cells andor said digital standard cells, and maps one or more said digital circuits, or portions thereof, to at least one of said digital standard cells andor said general type analog standard cells, said mapping occurring concurrently, serially, or in parallel;
places each said mapped general type analog standard cell, and places said said mapped digital standard cell, within a said layout row that has said row height equal to said cell height or across an integer number of adjacent said layout rows that has total height equal to said cell height, said placement occurring concurrently, serially, or in parallel; and
routes interconnect lines to and from said mapped general type analog standard cells, and routes interconnect lines to and from said mapped digital standard cells, said routing occurring concurrently, serially, or in parallel.
6. An SoC physical design flow including at least one standard cell library and defining one or more layout rows, wherein
said layout rows each have a specified row height;
said standard cell library includes at least one sourcedrain-shared type analog standard cell of claim 3 and zero or more digital standard cells;
each said sourcedrain-shared type analog standard cell has cell height equal to one of said row heights or to an integer multiple thereof; and
each said digital standard cell has cell height equal to one of said row heights or to an integer multiple thereof; wherein
said SoC physical design flow can accept as input an SoC design description comprising either or both analog circuits and digital circuits; and
said SoC physical design flow performs the following tasks:
maps one or more said analog circuits, or portions thereof, to at least one of said sourcedrain-shared type analog standard cells andor said digital standard cells, and maps one or more said digital circuits, or portions thereof, to at least one of said digital standard cells andor said sourcedrain-shared type analog standard cells, said mapping occurring concurrently, serially, or in parallel;
places each said mapped sourcedrain-shared type analog standard cell, and places said said mapped digital standard cell, within a said layout row that has said row height equal to said cell height or across an integer number of adjacent said layout rows that has total height equal to said cell height, said placement occurring concurrently, serially, or in parallel; and
routes interconnect lines to and from said mapped sourcedrain-shared type analog standard cells, and routes interconnect lines to and from said mapped digital standard cells, said routing occurring concurrently, serially, or in parallel.
7. The standard cell library of claim 1 comprising at least one general type analog standard cell of claim 2.
8. The standard cell library of claim 1 comprising at least one sourcedrain-shared type analog standard cell of claim 3
9. The standard cell library of claim 1 comprising at least one general type analog standard cell of claim 2 and at least one sourcedrain-shared type analog standard cell of claim 3.
10. The SoC physical design flow of claim 4 further comprising the library of claim 7.
11. The SoC physical design flow of claim 4 further comprising the library of claim 8.
12. The SoC physical design flow of claim 4 further comprising the library of claim 9.
13. The SoC physical design flow of claim 4 further comprising the library of claim 7 and the library of claim 8
14. The SoC physical design flow of claim 4 further comprising the library of claim 7 and the library of claim 9
15. The SoC physical design flow of claim 4 further comprising the library of claim 8 and the library of claim 9
16. The SoC physical design flow of claim 4 further comprising the library of claim 7, the library of claim 8, and the library of claim 9.