1. An apparatus, comprising:
a plurality of field-effect transistor (FET) structures stacked horizontally and vertically in a three-dimensional memory array architecture;
a plurality of gates extending vertically and spaced horizontally between the plurality of FET structures; and
a ferroelectric material separating the plurality of FET structures and the plurality of gates, wherein:
individual ferroelectric FETs (FeFETs) are located at intersections of the plurality of FET structures, the plurality of gates, and the ferroelectric material; and
the ferroelectric material is shared by FeFETs of a same vertical FeFET stack.
2. The apparatus of claim 1, wherein each FET structure of the plurality of FET structures includes a drain region, a body region, and a source region stacked in a verticalarrangement.
3. The apparatus of claim 2, further comprising a plurality of access lines coupled with individual FeFETs.
4. The apparatus of claim 3, wherein the plurality of access lines includes:
a plurality of word lines coupled to the plurality of gates; and
a plurality of bit lines coupled to the drain regions of the plurality of FET structures.
5. The apparatus of claim 4, wherein the plurality of word lines couple to the plurality of gates according to an alternating contact scheme.
6. The apparatus of claim 2, wherein each FET structure further comprises:
a drain contact coupled to the drain region; and
a source contact coupled to the source region, wherein the drain contact and the source contact are coupled on opposite ends of the three-dimensional memory array architecture.
7. The apparatus of claim 6, wherein the source contact is further coupled to the body region of the corresponding FET structure.
8. The apparatus of claim 1, wherein each gate of the plurality of gates has the ferroelectric material disposed on at least one side of the gate.
9. The apparatus of claim 1, wherein at least some of the gates of the plurality of gates have the ferroelectric material disposed on at least two sides of the gate.
10. An apparatus, comprising:
a first vertical ferroelectric field-effect transistor (FeFET) stack including a first plurality of gates separated from a first FET structure by a first ferroelectric material; and
a second vertical FeFET stack including a second plurality of gates separated from a second FET structure by a second ferroelectric material, wherein:
the first vertical FeFET stack and the second vertical FeFET stack are stacked horizontally and separated by a dielectric material; and
the first ferroelectric material is shared by FeFETs of the first vertical FeFET stack and the second ferroelectric material is shared by FeFETs of the second vertical FeFET stack.
11. The apparatus of claim 10, wherein the dielectric material includes a third ferroelectric material configured such that the second vertical FeFET stack has memory cells on both sides of the second FET structure of the second vertical FeFET stack.
12. The apparatus of claim 11, wherein neighboring gates from the first plurality of gates and the second plurality of gates along the same horizontal axis are part of the same word line.
13. The apparatus of claim 12, further comprising a plurality of word line parallel contacts that extend linearly across the first vertical FeFET stack and the second vertical FeFET stack, wherein a single word line contact couples the neighboring gates from the first plurality of gates and the second plurality of gates along the same horizontal axis.
14. The apparatus of claim 11, wherein neighboring gates from the first plurality of gates and the second plurality of gates along the same horizontal axis are part of different word lines.
15. The apparatus of claim 14, further comprising a plurality of additional vertical FeFET stacks that include additional pluralities of gates, the additional vertical FeFET stacks stacked horizontally with the first vertical FeFET stack and the second vertical FeFET stack.
16. The apparatus of claim 15, further comprising a plurality of mutually parallel word line contacts that extend along the first vertical FeFET stack, the second vertical FeFET stack, and the plurality of additional vertical FeFET stacks, wherein neighboring gates from the first plurality of gates and the second plurality of gates along the same horizontal axis couple to different ones of the mutually parallel word line contacts.
17. The apparatus of claim 16, wherein:
one of the neighboring gates extends to a first end of the first vertical FeFET stack, and couples with a first one of the mutually word line contact; and
another of the neighboring gates extends to a second end of the second vertical FeFET stack, and couples with a second one of the mutually word line contact.
18. The apparatus of claim 16, wherein the plurality of word line contacts are offset from the first plurality of gates and the second plurality of gates, and further extend linearly across the first vertical FeFET stack, the second vertical FeFET stack, and the plurality of additional vertical FeFET stacks.
19. The apparatus of claim 16, wherein the plurality of word line contacts each has an arcuate shape that extends around one of the neighboring gates.
20. The apparatus of claim 10, wherein the first vertical FeFET stack and the second vertical FeFET stack comprise a portion of a three dimensional memory array of the apparatus.
21. The apparatus of claim 20, wherein the three-dimensional memory array comprises at least a portion of a memory device of the apparatus.
22. The apparatus of claim 21, wherein the memory device comprises at least a portion of the apparatus.
23. The apparatus of claim 22, further comprising a control circuit operably coupled to the memory device, and configured to apply one or more voltages to perform operations on memory cells of the first vertical FeFET stack and the second vertical FeFET stack.
24. he apparatus of claim 23, further comprising an input device and an output device operably coupled to the control circuit.
25. An apparatus, comprising:
a ferroelectric field-effect transistor (FeFET) memory array having a plurality of FeFETs coupled at cross-points of a plurality of access lines, wherein the FeFET memory array is configured to have a substantially uniform series resistance for a current path for each FeFET of the plurality of FeFETs.
26. The apparatus of claim 25, further comprising:
a plurality of bit line contacts coupled to bit lines of the plurality of FeFETs;
a plurality of source line contacts coupled to source lines of the plurality of FeFETs; and
a plurality of word line contacts coupled to word lines of the plurality of FeFETs, wherein the bit line contacts and the source line contacts are coupled on opposing ends of the FeFET memory array.
27. An apparatus, comprising:
a three-dimensional memory array having a plurality of ferroelectric field-effect transistor (FeFET) memory cells located at intersections of ferroelectric material coupled with a plurality of bit lines and a plurality of word lines, wherein:
the plurality of FeFET memory cells are located along vertical strings of the three-dimensional memory array; and
the ferroelectric material is shared by the plurality of FeFET memory cells along the vertical strings.
28. The apparatus of claim 27, wherein each bit line of the plurality of bit lines are coupled to a drain region that has at least two sides coupled with the ferroelectric material such that each drain region is shared by neighboring gates to form the plurality of FeFET memory cells.
29. The apparatus of claim 28, wherein the neighboring gates and word lines are configured to independently access the plurality of FeFETs associated with the same bit line.
30. The apparatus of claim 27, wherein the vertical strings couple with memory cell gates coupled with the plurality of word lines.
31. The apparatus of claim 30, wherein the vertical strings each include a vertical channel surrounded by the ferroelectric material.
32. A method of operating a three-dimensional ferroelectric field-effect transistor (FeFET) memory array, the method comprising:
applying a combination of voltages to a plurality of word lines and digit lines for a desired operation for a plurality of FeFET memory cells of a three-dimensional FeFET memory array, at least one digit line having a plurality of FeFET memory cells accessible by neighboring gates through shared ferroelectric material.
33. The method of claim 32, wherein applying a combination of voltages comprises employing a selection scheme from the group consisting of a V3 selection scheme and a V2 selection scheme.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for assessing risk on a project associated with at least one change proposal directed toward the project, the project being developed by a service provider for a client, said method comprising:
receiving, from the client by the service provider, the at least one change proposal directed toward the project during a life cycle of the project, the change proposal requesting at least one amendment to be performed to the project being developed by the service provider;
identifying, based on the at least one amendment request, at least one artifact of the project to be potentially affected upon the change proposal being adopted; and
generating at least one metric indicative of the potential effects on the project based on said identifying the at least one artifact, the at least one metric providing an objective risk assessment for the service provider to provide the client and for allowing the service provider and the client to assess both direct and indirect risk before the at least one change proposal is adopted and to objectively make an informed business decision as to whether or not to adopt the at least one change proposal.
2. The method according to claim 1, wherein the at least one metric includes a statistical value.
3. The method according to claim 1, wherein said generating includes performing a regression analysis.
4. The method according to claim 1, wherein the service provider is at least one of a consultant and a contractor.
5. The method according to claim 1, wherein the project is at least one of a document and a product.
6. The method according to claim 1, wherein said identifying includes determining an artifact to be amended.
7. The method according to claim 6 wherein said identifying the at least one artifact includes counting descendants of the artifact to be amended.
8. The method according to claim 1, wherein the at least one metric includes a numerical representation of at least one of direct and indirect artifacts affected by the change proposal.
9. The method according to claim 1, wherein the project is a requirements specification.
10. A system for assessing risk on a project associated with at least one change proposal directed toward the project, the project being developed by a service provider for a client, said system comprising:
means for receiving, from the client by the service provider, the at least one change proposal directed toward the project during a life cycle of the project, the at least one change proposal requesting at least one amendment to be performed to the project being developed by the service provider;
means for identifying, based on the at least one amendment request, at least one artifact of the project to be potentially affected upon the change proposal being adopted; and
means for generating at least one metric indicative of the potential effects on the project based on said identifying the at least one artifact, the at least one metric providing an objective risk assessment for the service provider to provide the client and for allowing the service provider and the client to assess both direct and indirect risk before the at least one change proposal is adopted and to objectively make an informed business decision as to whether or not to adopt the at least one change proposal.
11. The system according to claim 10, wherein the at least one metric includes a statistical value.
12. The system according to claim 10, wherein the means for generating includes performing a regression analysis.
13. The system according to claim 10, wherein the service provider is at least one of a consultant and a contractor.
14. The system according to claim 10, wherein the project is at least one of a document and a product.
15. The system according to claim 10, wherein the project is a requirements specification.
16. The system according to claim 10, wherein the means for identifying includes determining an artifact to be amended.
17. The system according to claim 16, wherein the means for identifying the at least one artifact includes counting descendants of the artifact to be amended.
18. The system according to claim 10, wherein the at least one metric includes a numerical representation of at least one of direct and indirect artifacts affected by the change proposal.
19. A computer-readable medium having stored thereon sequences of instructions, the sequences of instructions, when executed by a processor, causes the processor to:
receive, from a client by a service provider, at least one change proposal directed toward a project during a life cycle of the project, the project being developed by the service provider for the client, the at least one change proposal requesting at least one amendment to be performed to the project;
identify, based on the at least one amendment request, at least one artifact of the project to be potentially affected upon the change proposal being adopted; and
generate at least one metric indicative of the potential effects on the project based on said identifying the at least one artifact, the at least one metric providing an objective risk assessment for the service provider to provide the client and for allowing the service provider and the client to assess both direct and indirect risk before the at least one change proposal is adopted and to objectively make an informed business decision as to whether or not to adopt the at least one change proposal.