1. An automatic weight and measures computing device comprising:
a storage unit for storing a plurality of operational formulas, each operational formula being composed of at least two parameters and at least one logical operator;
an input device comprising:
a set of number buttons for inputting at least one number;
a set of symbol buttons for inputting at least one logical operator;
a set of selection buttons for selecting an operational formula; and
a confirmation button for confirming input data;
a display unit comprising:
a value display area for displaying values; and
a formula display area for displaying the selected operational formula; and
a control unit for executing a mathematical operational formula;
wherein the automatic weight and measures computing device is characterized in that the input unit inputs values corresponding to parameters according to the selected operational formula, and then the control unit provides an operational result according to the selected operational formula and the input values and displays the operational result in the value display area.
2. The automatic weight and measures computing device as claimed in claim 1, wherein the input unit is connected to a measuring unit for receiving the value measured by the measuring unit.
3. The automatic weight and measures computing device as claimed in claim 1, wherein the display unit includes a graphical display area for displaying a target object corresponding to the operational formula.
4. The automatic weight and measures computing device as claimed in claim 1, wherein the formula display area is used for displaying definitions of the parameters of the operational formula.
5. The automatic weight and measures computing device as claimed in claim 1, wherein in the formula display area, a confirmed input parameter is underlined.
6. The automatic weight and measures computing device as claimed in claim 1, wherein the control unit has an error detection means, and after the error detection means verifies all of the input values corresponding to the operational formula, the control unit then calculates an operational result according to the operational formula and the input values.
7. The automatic weight and measures computing device as claimed in claim 1, wherein the input unit comprises a mode switching button for switching into a formula mode for the operational formula selected by the selection buttons.
8. The automatic weight and measures computing device as claimed in claim 1, wherein the input unit comprises a unit transformation button for converting the values into different values corresponding to a unit used in the operational formula.
9. An automatic weight and measures computing method comprising the steps of:
(A) receiving an input signal of a selected operational formula;
(B) receiving at least two parameters and at least one logical operator defined by the operational formula;
(C) displaying the operational formula;
(D) receiving input signals corresponding to values for the parameters;
(E) determining a result according to the operational formula and the input values; and
(F) displaying the result.
10. The automatic weight and measures computing method as claimed in claim 9, wherein step (A) further comprises: receiving an input signal of a selected graphic, the graphic corresponding to an operational formula.
11. The automatic weight and measures computing method as claimed in claim 9, wherein in step (D), the input signals of the values are measurement values provided by a measuring device.
12. The automatic weight and measures computing method as claimed in claim 9, wherein step (E) further comprises: determining a result according to the operational formula and the input values.
13. The automatic weight and measures computing method as claimed in claim 9, wherein confirmed input parameters are underlined.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A memory system comprising:
a memory controller coupled to a bus;
a memory module comprising N memory devices coupled to the bus, each one of the N memory devices operable to receive data from the bus during a write operation and to transmit data onto the bus during a read operation;
wherein the memory controller comprises:
a tracking circuit operable to track a number of memory device operations in M of the N memory devices during a period of time, where M is less than or equal to N; and
a control circuit operable to manipulate operation of the memory system in response to a comparison of the number of memory operations and a reference.
2. The memory system of claim 1, wherein the tracking circuit comprises at least one counter.
3. The memory system of claim 2, wherein the at least one counter comprises:
a first counter incremented by each read operation during the period of time; and
a second counter incremented by each write operation during the period of time.
4. The memory system of claim 3, wherein the at least one counter comprises a First-In-First-Out (FIFO) buffer.
5. The memory system of claim 1, wherein the reference comprises power value data relating a number of memory device operations with an estimated operating temperature for the M memory devices.
6. The memory system of claim 5, wherein the power value data is stored in the memory controller.
7. The memory system of claim 5, wherein the power value data is stored in one or more register on the N memory devices.
8. The memory system of claim 5, wherein the memory module further comprises a data storage element storing the power value data for the M memory devices.
9. The memory system of claim 5, wherein the memory controller further comprises:
a delay circuit operable to select a first delay between successive read operations to the M memory devices and to select a second delay between successive write operations to the M memory devices on the basis of a control circuit comparison indicating that the number of memory operations exceeds the reference.
10. The memory system of claim 5, wherein each of the N memory devices is operable in first and second modes of operation, wherein each of the N memory devices consumes less power in the second mode of operation as compared with the first mode of operation; and
wherein the memory controller is operable to select between the first and second modes of operation for each one of the M memory devices on the basis of the control circuit comparison.
11. A method of regulating the operating temperature of memory devices in a memory system comprising; a memory controller and a memory module comprising a plurality of memory devices, the method comprising:
determining a number of operations involving one or more memory devices on the memory module during a time period;
comparing the number of operations to reference data corresponding to an estimated operating temperature the one or more memory devices;
determining whether to manipulate the operation of the memory system on the basis of the comparison between the number of operations and the reference data.
12. The method of claim 11, wherein the number of operations comprises at least one of a number of read operations involving the one or more memory devices, a number of write operations involving the one or more memory devices, and a number of refresh operations involving the one or more memory device.
13. The method of claim 11, further comprising:
upon determining to manipulate the operation of the memory system, introducing delays between successive read operations and successive write operations to the one or memory devices.
14. The method of claim 11, further comprising:
upon determining to manipulate the operation of the memory system, placing the one or more memory devices in a mode of operation requiring less power.
15. The method of claim 11, further comprising:
upon determining to manipulate the operation of the memory system, increasing the refresh rate for the one or more memory device.
16. A memory system comprising:
a memory controller coupled to a bus;
a memory module comprising N memory devices coupled to the bus, each one of the N memory devices having a maximum operating temperature;
at least one temperature sensor measuring an actual operating temperature for M of the N memory devices, where M is less than or equal to N; and
a circuit periodically refreshing data in the M memory devices at a first rate when the actual operating temperature is below the maximum operating temperature, and at a second rate, higher than the first rate, when the actual operating temperature is above the maximum operating temperature.
17. The memory system of claim 16, wherein the at least one temperature sensor generates temperature data communicated to the memory controller via the bus.
18. The memory system of claim 16, wherein the at least one temperature sensor generates temperature data, and wherein the memory system further comprises a signal line outside the bus connecting the at least one temperature sensor and the memory controller, such that the temperature data is communicated to the memory controller via the signal line.
19. The memory system of claim 18, wherein the temperature data comprises a digital flag and wherein the memory controller further comprises a data register connected to the signal line and storing a value associated with the digital flag.
20. The memory system of claim 16 wherein the memory module further comprises a heat spreader, and wherein at least one temperature sensor is associated with either each one of the M memory devices, or a thermocouple between each one of the M memory devices and the heat spreader.
21. A memory system comprising:
a memory module comprising N memory devices coupled to a bus, each one of the N memory devices being operable in at least a first power mode and a second power mode, and having a maximum threshold temperature;
at least one temperature sensors measuring actual operating temperature for a group M of the N memory devices, where M is less than or equal to N;
a memory controller coupled to the bus, the memory controller selecting the first power mode for each memory device in the group M having an actual operating temperature below the maximum threshold temperature, and selecting the second power mode for each memory device in the group M having an actual operating temperature above the maximum threshold temperature;
wherein each one of the N memory device consumes less power in the second power mode than in the first power mode.
22. The memory system of claim 21, wherein the at least one temperature sensor generates temperature data communicated to the memory controller via the bus.
23. The memory system of claim 21, wherein the at least one temperature sensor generates temperature data, and wherein the memory system further comprises a signal line outside the bus connecting the at least one temperature sensor and the memory controller, such that the temperature data is communicated to the memory controller via the signal line.
24. The memory system of claim 23, wherein the temperature data comprises a digital flag and wherein the memory controller further comprises a data register connected to the signal line and storing a value associated with the digital flag.
25. A method of regulating the operating temperature of memory devices in a memory system comprising a memory controller and a memory module comprising N memory devices, the method comprising:
storing power value data indicative of a maximum threshold temperature for at least one of the N memory devices in a data storage element associated with the memory module;
tracking a number of memory system operations involving M of the N memory devices during a time period, where M is less than or equal to N and where the number of operations is indicative of an estimated operating temperature for the M memory devices;
comparing the number of memory system operations to the power value data; and
upon determining based on the comparison of the number of memory system operations to the power value data that the estimated operating temperature for the M memory devices is greater than the maximum threshold temperature, manipulating the operation of the memory system to reduce the operating temperature of the M memory devices.
26. The method of claim 25, further comprising:
reading the power value data from the data storage element during memory system initialization.
27. The method of claim 25, wherein the data storage element is a serial presence detect device.