1. An exhaust system comprising:
an exhaust pipe through which an exhaust gas flows, the exhaust gas being generated by an engine having a first injector injecting a fuel into a combustion chamber;
a second injector mounted at the exhaust pipe and injecting a reducing agent;
a DeNOx catalyst mounted at the exhaust pipe downstream of the second injector and reducing NOx contained in the exhaust gas by using the reducing agent injected by the second injector; and
a control unit controlling the second injector so as to regenerate the DeNOx catalyst and calculating mass of NO2 and mass of the NOx remaining in the DeNOx catalyst after regeneration,
wherein the control unit calculates total mass flow of the reducing agent used in the regeneration of the DeNOx catalyst, calculates each mass flow of the reducing agent used respectively in nitrate reduction reaction, NO2 reduction reaction, and simple oxidation reaction of the reducing agent, and calculates mass flow of the NO2 released from the DeNOx catalyst and mass flow of reduced NO2 by using each mass flow of the reducing agent.
2. The exhaust system of claim 1, wherein the control unit calculates mass flow of the NO2 slipped from the DeNOx catalyst from NO2 slip efficiency, mass of the NO2 stored in the DeNOx catalyst, and temperature of the DeNOx catalyst.
3. The exhaust system of claim 2, wherein the control unit calculates the mass of the NO2 and the mass of the NOx remaining in the DeNOx catalyst after the regeneration from the mass flow of the NO2 released from the DeNOx catalyst, the mass flow of the reduced NO2, and the mass flow of the slipped NO2.
4. The exhaust system of claim 1, wherein the control unit calculates the total mass flow of the reducing agent from utilization efficiency of the reducing agent and mass flow of the injected reducing agent.
5. The exhaust system of claim 4, wherein the control unit calculates the utilization efficiency of the reducing agent from mass flow of the exhaust gas and aging of the DeNOx catalyst.
6. The exhaust system of claim 1, wherein the control unit calculates the mass flow of the reducing agent used in the nitrate reduction reaction from the temperature of the DeNOx catalyst, a lambda of an inlet of the DeNOx catalyst, the mass of the NOx stored in the DeNOx catalyst, and the total mass flow of the reducing agent.
7. The exhaust system of claim 1, wherein the control unit calculates the mass flow of the reducing agent used in the NO2 reduction reaction from the mass of the NO2 stored in the DeNOx catalyst, the temperature of the DeNOx catalyst, and the total mass flow of the reducing agent.
8. The exhaust system of claim 1, wherein the control unit calculates the mass flow of the reducing agent used in the simple oxidation reaction of the reducing agent from the temperature of the DeNOx catalyst, a lambda of an engine outlet, and the total mass flow of the reducing agent.
9. The exhaust system of claim 1, wherein the control unit calculates the NO2 slip efficiency from the aging of the DeNOx catalyst, initial slip efficiency of the DeNOx catalyst, and slip efficiency of the aged DeNOx catalyst.
10. The exhaust system of claim 1, wherein the reducing agent is a fuel, and
wherein the exhaust system is mounted on the exhaust pipe between the second injector and the DeNOx catalyst and further comprises a fuel cracking catalyst for decomposing the fuel.
11. A method for predicting regeneration of a DeNOx catalyst, comprising:
determining total mass flow of a reducing agent;
determining mass flow of the reducing agent used in a nitrate reduction reaction, mass flow of the reducing agent used in a NO2 reduction reaction, and mass flow of the reducing agent which is simply oxidized by using a total mass flow of the reducing agent;
determining mass flow of released NO2 and mass flow of reduced NO2 by using the mass flow of the reducing agent used in the nitrate reduction reaction and the mass flow of the reducing agent used in the NO2 reduction reaction;
determining mass flow of NO2 slipped from DeNOx catalyst;
determining mass of NO2 and mass of NOx remaining at the DeNOx catalyst after regeneration based on the mass flow of the released NO2, the mass flow of the reduced NO2, and the mass flow of the slipped NO2; and
initiating a subsequent regeneration of the DeNOx catalyst based on the remaining NOx mass value and NOx mass value.
12. The method of claim 11, wherein the total mass flow of the reducing agent is determined by using utilization efficiency of the reducing agent and mass flow of the injected reducing agent.
13. The method of claim 12, wherein the utilization efficiency of the reducing agent is determined by using mass flow of an exhaust gas and aging of the DeNOx catalyst.
14. The method of claim 11, wherein the mass flow of the reducing agent used in the nitrate reduction reaction is determined by using temperature of the DeNOx catalyst, a lambda of an inlet of the DeNOx catalyst, the mass of the NOx stored in the DeNOx catalyst, and the total mass flow of the reducing agent.
15. The method of claim 11, wherein the mass flow of the reducing agent used in the NO2 reduction reaction is determined by using the mass of the NO2 stored in the DeNOx catalyst, the temperature of the DeNOx catalyst, and the total mass flow of the reducing agent.
16. The method of claim 11, wherein the mass flow of the reducing agent which is simply oxidized is determined by using the temperature of the DeNOx catalyst, a lambda of an engine outlet, and the total mass flow of the reducing agent.
17. The method of claim 11, wherein the mass flow of the NO2 slipped from the DeNOx catalyst is determined by using NO2 slip efficiency, the mass of the NO2 stored in the DeNOx catalyst, and the temperature of the DeNOx catalyst.
18. The method of claim 17, wherein the NO2 slip efficiency is determined by using the aging of the DeNOx catalyst, initial slip efficiency of the DeNOx catalyst, and slip efficiency of the aged DeNOx catalyst.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A switching transistor driver circuit in which a series junction between a high-side switching transistor on a high potential side and a low-side switching transistor on a low potential side is an output terminal, the high-side switching transistor is switched based on a control pulse signal of an output of a high side circuit, and the low-side switching transistor is switched based on a control pulse signal of an output of a low side circuit, so that power supply to the output terminal is controlled,
wherein the low side circuit is switched based on a second input pulse signal fed to a low side input terminal and generates the control pulse signal for turning onoff the low side switching transistor, and
the high side circuit is configured such that a latch circuit is setreset by each edge detection pulse having detected leading edge and trailing edge of a first input pulse signal fed to a high side input terminal, the control pulse signal for turning onoff the high-side switching transistor is generated, and the latch circuit is reset in one of a period during which a terminal voltage of the output terminal is inverted or a period immediately after the inversion.
2. The switching transistor driver circuit according to claim 1, wherein the latch circuit is reset when the low-side switching transistor is turned on after the high-side switching transistor is turned off or in a period during which current passes through the output terminal from the low-side switching transistor after the high-side switching transistor is turned off.
3. The switching transistor driver circuit according to claim 1, wherein the low side circuit comprises:
a delay circuit which is disposed on a path from the low side input terminal to the low-side switching transistor to make a correction of a signal delay time in the high side circuit and contributes to formation of the control pulse signal for turning onoff the low-side switching transistor,
a reset pulse generation circuit for preventing a malfunction, the reset pulse generation circuit delaying the second input pulse signal fed from the low side input terminal and generating a reset signal for the high side circuit,
the high side circuit comprises:
a first edge detection circuit for detecting the leading edge of the first input pulse signal and a second edge detection circuit for detecting the trailing edge of the first input pulse signal,
the latch circuit has a set input and a reset input respectively fed with signals obtained by changing, in a level shift circuit, a voltage level of an edge signal outputted from the first edge detection circuit and a voltage level of an edge signal outputted from the second edge detection circuit, the reset input being also fed with a signal obtained by changing, in the level shift circuit, a voltage level of the output signal from the reset pulse generation circuit,
the latch circuit has a minimum reference potential terminal connected to a low potential side of the high-side switching transistor, and the high-side switching transistor is driven based on an output signal from the latch circuit.
4. The switching transistor driver circuit according to claim 3, wherein the level shift circuit changes the voltage level of the output signal from the reset pulse generation circuit and the voltage levels of the first and second edge signals outputted from the first and second edge detection circuits.
5. The switching transistor driver circuit according to claim 3, wherein the reset pulse generation circuit generates a reset signal for the latch circuit in synchronization with one of a leading edge or a trailing edge of the second input pulse signal in one of a period during which the terminal voltage of the output terminal is inverted or a period immediately after the inversion.
6. The switching transistor driver circuit according to claim 3, wherein the reset pulse generation circuit is fed with an output signal of the first delay circuit as an input signal,
the delay circuit is made up of the first delay circuit fed with the second input pulse signal as an input signal and a second delay circuit fed with the output signal of the first delay circuit as an input signal, and the low-side switching transistor is driven based on an output signal of the second delay circuit.
7. The switching transistor driver circuit according to claim 3, wherein the delay circuit is made up of first and second delay circuits, each being fed with the second input pulse signal as an input signal,
the reset pulse generation circuit is fed with an output signal of the first delay circuit having a shorter delay time than the second delay circuit, and
the low-side switching transistor is driven based on an output signal of the second delay circuit.
8. The switching transistor driver circuit according to claim 3, further comprising a delay circuit between inputs of the first and second edge detection circuits and the high side input terminal.
9. The switching transistor driver circuit according to claim 3, wherein in one of a period during which the terminal voltage of the output terminal is inverted or a period immediately after the inversion, a generator of a reset signal inputted to the latch circuit sets timing of start of reset in response to the signal from the second edge detection circuit for switching the high-side switching transistor from on to off, the reset is completed in synchronization with one of a leading edge or a trailing edge of the second input pulse signal, a reset pulse width serving as a reset period is set by the output signal of the reset pulse generation circuit, and
a continuous reset pulse signal is generated by delaying a rear edge of the output signal of the second edge detection circuit for detecting the trailing edge of the first input pulse signal or advancing a front edge of a reset pulse signal of an output of the reset pulse generation circuit.
10. The switching transistor driver circuit according to claim 1, further comprising:
a delay circuit constructed on a path from the low side input terminal to the low-side switching transistor,
a reset pulse generation circuit for preventing a malfunction, the reset pulse generation circuit being fed with an input signal from the delay circuit, and
a first edge detection circuit for detecting the leading edge of the first input pulse signal,
wherein the latch circuit has a set input fed with a signal obtained by changing, in a level shift circuit, a voltage level of an edge signal outputted from the first edge detection circuit and a reset input fed with a signal obtained by changing, in the level shift circuit, a voltage level of an output signal from the reset pulse generation circuit,
the latch circuit has a minimum reference potential terminal connected to the low potential side of the high-side switching transistor, and
the high-side switching transistor is driven based on an output signal from the latch circuit.
11. The switching transistor driver circuit according to claim 10, wherein the reset pulse generation circuit generates a reset signal for the latch circuit in synchronization with one of a leading edge or a trailing edge of the second input pulse signal in one of a period during which the terminal voltage of the output terminal is inverted or a period immediately after the inversion.
12. The switching transistor driver circuit according to claim 10, wherein the reset pulse generation circuit is fed with an output signal of the first delay circuit as an input signal,
the delay circuit is made up of the first delay circuit fed with the second input pulse signal as an input signal and a second delay circuit fed with the output signal of the first delay circuit as an input signal, and the low-side switching transistor is driven based on an output signal of the second delay circuit.
13. The switching transistor driver circuit according to claim 10, wherein the delay circuit is made up of first and second delay circuits, each being fed with the second input pulse signal as an input signal,
the reset pulse generation circuit is fed with an output signal of the first delay circuit having a shorter delay time than the second delay circuit, and
the low-side switching transistor is driven based on an output signal of the second delay circuit.
14. The switching transistor driver circuit according to claim 1, further comprising:
a first delay circuit constructed on a path from the low side input terminal to the low-side switching transistor,
a first edge detection circuit for detecting the leading edge of the pulse signal fed to the high side input terminal, and
a second edge detection circuit for detecting the trailing edge of the pulse signal fed to the high side input terminal,
wherein the latch circuit has a minimum reference potential terminal connected to a low potential side of the high-side switching transistor,
the latch circuit has a set input and a reset input respectively fed with signals obtained by changing, in a level shift circuit, a voltage level of an edge signal outputted from the first edge detection circuit and a voltage level of an edge signal outputted from the second edge detection circuit, the high-side switching transistor is driven based on the output signal of the latch circuit, and
the signal from the second edge detection circuit is inputted as a reset signal to the latch circuit by delaying the signal from the second edge detection circuit or delaying a rear edge of the signal from the second edge detection circuit, the rear edge indicating timing of end of reset, in one of a period during which the terminal voltage of the output terminal is inverted or a period immediately after the inversion.
15. A switching transistor driver circuit in which a series junction between a high-side switching transistor on a high potential side and a low-side switching transistor on a low potential side is an output terminal, the high-side switching transistor is switched based on a control pulse signal of an output of a high side circuit, and the low-side switching transistor is switched based on a control pulse signal of an output of a low side circuit, so that power supply to the output terminal is controlled,
the switching transistor driver circuit comprising:
a first delay circuit constructed on a path from a low side input terminal to the low-side switching transistor,
a first edge detection circuit for detecting a leading edge of a pulse signal fed to a high side input terminal, and
a second edge detection circuit for detecting a trailing edge of the pulse signal fed to the high side input terminal,
wherein the latch circuit has a minimum reference potential terminal connected to a low potential side of the high-side switching transistor,
the latch circuit has a set input and a reset input respectively fed with signals obtained by changing, in a level shift circuit, a voltage level of an edge signal outputted from the first edge detection circuit and a voltage level of an edge signal outputted from the second edge detection circuit, the high-side switching transistor is driven based on an output signal of the latch circuit, and
in a period during which the high-side switching transistor is turned off by the pulse signal fed to the high side input terminal, the set input to the latch circuit is prohibited on an input side of the level shift circuit by using one of a first period during which a signal for turning on the low-side switching transistor is inputted from the low side input terminal and a second period obtained by delaying the first period.
16. A switching transistor driver circuit in which a series junction between a high-side switching transistor on a high potential side and a low-side switching transistor on a low potential side is an output terminal, the high-side switching transistor is switched based on a control pulse signal of an output of a high side circuit, and the low-side switching transistor is switched based on a control pulse signal of an output of a low side circuit, so that power supply to the output terminal is controlled,
the switching transistor driver circuit comprising:
a first delay circuit constructed on a path from a low side input terminal to the low-side switching transistor,
a first edge detection circuit for detecting a leading edge of a pulse signal fed to a high side input terminal, and a second edge detection circuit for detecting a trailing edge of the pulse signal fed to the high side input terminal,
wherein the latch circuit has a minimum reference potential terminal connected to a low potential side of the high-side switching transistor,
the latch circuit has a set input and a reset input respectively fed with signals obtained by changing, in a level shift circuit, a voltage level of an edge signal outputted from the first edge detection circuit and a voltage level of an edge signal outputted from the second edge detection circuit, the high-side switching transistor is driven based on an output signal of the latch circuit, and
in a period during which the low-side switching transistor is turned off by a pulse signal fed to the low side input terminal, an on signal to the low-side switching transistor is prohibited on an input path from an output of the first delay circuit to the low-side switching transistor by using one of a third period during which the pulse signal fed from the high side input terminal is inputted to turn on the high-side switching transistor or a fourth period obtained by delaying the third period.