1. A nonvolatile memory device comprising:
a nonvolatile memory cell array;
an x-selector configured to select a plurality of memory cells among the nonvolatile memory cell array based on an address; and
a page buffer configured to read user data from the plurality of memory cells,
a peripheral circuit configured to receive a command, to select one of a single data rate (SDR) mode and a double data rate (DDR) mode in response to the command, and to receive a first signal toggling between a high level and a low level;
wherein, in the SDR mode, when data is output in synchronization with the first signal, the data is maintained with the same value at a rising edge and a falling edge of each of a plurality of periods of the first signal during a data output cycle,
in the DDR mode, the data is output in synchronization with both the rising edge and the falling edge of the first signal during the data output cycle,
the peripheral circuit is configured to output identification data only in the SDR mode,
the peripheral circuit is configured to output the user data in both the SDR mode and the DDR mode, and
the identification data includes at least one of a maker code, a device code, a page size and a block size of the nonvolatile memory device.
2. The nonvolatile memory device of claim 1, wherein in the DDR mode, the data has a different value at the rising edge and the falling edge of at least one period among the plurality of periods of the first signal.
3. The nonvolatile memory device of claim 1, wherein the peripheral circuit is configured to receive a third signal toggling between a high level and a low level and to receive the address in synchronization with one of the rising edge and the falling edge of the third signal during an address input cycle regardless of the SDR mode and the DDR mode.
4. The nonvolatile memory device of claim 3, wherein the third signal is deactivated not to toggle after the address input cycle ends.
5. The nonvolatile memory device of claim 1, wherein the peripheral circuit is configured to generate a second signal by delaying the first signal in the DDR mode, the second signal being toggled between a high level and a low level.
6. The nonvolatile memory device of claim 5, wherein the peripheral circuit does not generate the second signal in the SDR mode.
7. The nonvolatile memory device of claim 3, wherein the user data, and the identification data are output through inputoutput pins and the address is received through the inputoutput pins.
8. The nonvolatile memory device of claim 7, wherein the peripheral circuit is configured to receive the command in synchronization with one of the rising edge and the falling edge of the third signal during a command input cycle regardless of the SDR mode and the DDR mode.
9. The nonvolatile memory device of claim 8, wherein the peripheral circuit is configured to receive a CLE signal through a CLE pin, the CLE signal being activated during the command input cycle, the peripheral circuit is configured to receive a ALE signal through a ALE pin, the ALE signal being activated during an address input cycle.
10. A storage device comprising:
a controller configured to output a command selecting one of a single data rate (SDR) mode and a double data rate (DDR) mode, an output address and a first signal toggling between a high level and a low level; and
a nonvolatile memory device including a nonvolatile memory cell array, the nonvolatile memory device being configured to read user data from the nonvolatile memory cell array based on the address, to receive the command to select one of the SDR mode and the DDR mode, and to receive the first signal during a data output cycle,
wherein, in the SDR mode, when data is output in synchronization with the first signal, the data is maintained with the same value at a rising edge and a falling edge of each of a plurality of periods of the first signal during the data output cycle,
in the DDR mode, the data is output in synchronization with both the rising edge and the falling edge of the first signal during the data output cycle,
the nonvolatile memory device is configured to output the user data in both the SDR mode and the DDR mode,
the nonvolatile memory device is configured to output identification data only in the SDR mode, and
the identification data includes at least one of a maker code, a device code, a page size and a block size of the nonvolatile memory device.
11. The storage device of claim 10, wherein in the DDR mode, the data has a different value at the rising edge and the falling edge of at least one period among the plurality of periods of the first signal.
12. The storage device of claim 10, wherein the controller is configured to provide to the nonvolatile memory device a third signal toggling between a high level and a low level and the address in synchronization with one of the rising edge and the falling edge of the third signal during an address input cycle regardless of the SDR mode and the DDR mode, and
the third signal is deactivated not to toggle after the address input cycle ends.
13. The storage device of claim 10, wherein the nonvolatile memory device is configured to generate a second signal by delaying the first signal in the DDR mode.
14. The storage device of claim 13, wherein the nonvolatile memory device does not generate the second signal in the SDR mode.
15. The storage device of claim 11, wherein the user data, and the identification data are output through inputoutput pins and the address is received through the inputoutput pins.
16. A method for operating a storage device including a nonvolatile memory device and a controller, the method comprising:
executing the storage device power-up;
providing, by the controller, a first signal toggling between a high level and a low level and an identification data read request to the nonvolatile memory device;
providing, by the nonvolatile memory device, identification data in synchronization with the first signal to the controller in response to the identification data read request;
providing, by the controller, a first command setting the nonvolatile memory device to a single data rate (SDR) mode;
providing, by the nonvolatile memory device, first data in synchronization with one of a rising edge and a falling edge of the first signal to the controller based on the first command;
providing, by the controller, a second command setting the nonvolatile memory device to a double data rate (DDR) mode;
providing, by the nonvolatile memory device, a second signal to the controller; and
providing, by the nonvolatile memory device, second data in synchronization with both a rising edge and a falling edge of the second signal to the controller based on the second command,
wherein the identification data includes at least one of a maker code, a device code, a page size and a block size of the nonvolatile memory device,
the second signal is generated by delaying the first signal and is toggled between a high level and a low level, and
the identification data is maintained with the same value at the rising edge and the falling edge within each period of the first signal.
17. The method of claim 16, further comprising:
providing, by the controller, a third signal toggling between a high level and a low level and the address in synchronization with one of the rising edge and the falling edge of the third signal during an address input cycle regardless of the SDR mode and the DDR mode to the nonvolatile memory device.
18. The method of claim 17, wherein the first command and the second command are received in synchronization with one of the rising edge and the falling edge of the third signal during a command input cycle regardless of the SDR mode and the DDR mode.
19. The method of claim 16, wherein the second signal is not generated in the SDR mode.
20. The method of claim 16, wherein the user data, and the identification data are output through inputoutput pins and the address is received through the inputoutput pins.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of optimizing illumination for a full-chip layer, comprising the steps of:
determining a pitch frequency of the full-chip layer, the pitch frequency indicating how often a pitch occurs in the full-chip layer so as to generate a pitch frequency histogram of the full-chip layer;
equating the pitch frequency histogram to be the first eigenfunction of the sum of coherent systems representation of a transformation cross coefficient; and
solving an integral equation for the first eigenfunction of the transformation cross coefficient so as to define the optimal illumination for the full-chip layer.
2. The method according to claim 1, wherein all pitches are equally weighted in the pitch frequency histogram.
3. The method according to claim 1, wherein the integral equation for the first eigenfunction of the transformation cross coefficient is solved such that the first eigenfunction becomes substantially identical to the pitch frequency.
4. The method according to claim 3, wherein a difference between the pitch frequency and the first eigenfunction is minimized by using a merit function to solve the integral equation for the first eigenfunction of the transformation cross coefficient.
5. The method according to claim 1, wherein the merit function is essentially the convolution of the first eigenfunction with the pitch frequency.
6. The method according to claim 1, wherein the integral equation for the first eigenfunction of the transformation cross coefficient is solved such that the first eigenfunction has a value of one for every non-zero value in the pitch frequency.
7. The method according to claim 1, wherein the pitch frequency is obtained by determining the separation between adjacent features on the full-chip layer that are within a coherence radius.
8. The method according to claim 1, wherein the pitch frequency is obtained by representing adjacent features on the full-chip layer with Dirac delta functions and measuring separation between the Dirac delta functions.
9. The method according to claim 1, wherein the pitch frequency for a random hole pattern or for a periodic hole pattern is obtained as a function of hole separation and as a function of angular separation.
10. The method according to claim 1, further comprising:
determining whether pitch frequencies fall into a negative region of the first eigenfunction by using the optimized illumination;
separating the pitch frequencies which fall into the negative region into another layer to be imaged with a second exposure; and
optimizing illumination for said another layer.
11. A computer program product having a computer readable medium bearing a computer program for optimizing illumination for a full-chip layer, the computer program, which executed, causing a computer to perform the steps of:
determining a pitch frequency of the full-chip layer, the pitch frequency indicating how often a pitch occurs in the full-chip layer so as to generate a pitch frequency histogram of the full-chip layer;
equating the pitch frequency histogram to be the first eigenfunction of the sum of coherent systems representation of a transformation cross coefficient; and
solving an integral equation for the first eigenfunction of the transformation cross coefficient so as to define the optimal illumination for the full-chip layer.
12. The computer program product according to claim 11, wherein all pitches are equally weighted in the pitch frequency histogram.
13. The computer program product according to claim 11, wherein the integral equation for the first eigenfunction of the transformation cross coefficient is solved such that the first eigenfunction becomes substantially identical to the pitch frequency.
14. The computer program product according to claim 13, wherein a difference between the pitch frequency and the first eigenfunction is minimized by using a merit function to solve the integral equation for the first eigenfunction of the transformation cross coefficient.
15. The computer program product according to claim 11, wherein the merit function is essentially the convolution of the first eigenfunction with the pitch frequency.
16. The computer program product according to claim 11, wherein the integral equation for the first eigenfunction of the transformation cross coefficient is solved such that the first eigenfunction has a value of one for every non-zero value in the pitch frequency.
17. The computer program product according to claim 11, wherein the pitch frequency is obtained by determining the separation between adjacent features on the full-chip layer that are within a coherence radius.
18. The computer program product according to claim 11, wherein the pitch frequency is obtained by representing adjacent features on the full-chip layer with Dirac delta functions and measuring separation between the Dirac delta functions.
19. The computer program product according to claim 11, wherein the pitch frequency for a random hole pattern or for a periodic hole pattern is obtained as a function of hole separation and as a function of angular separation.
20. The computer program product according to claim 11, further comprising:
determining whether pitch frequencies fall into a negative region of the first eigenfunction by using the optimized illumination;
separating the pitch frequencies which fall into the negative region into another layer to be imaged with a second exposure; and
optimizing illumination for said another layer.
21. An apparatus for optimizing illumination for a full-chip layer, comprising:
a first unit configured for determining a pitch frequency of the full-chip layer, the pitch frequency indicating how often a pitch occurs in the full-chip layer so as to generate a pitch frequency histogram of the full-chip layer;
a second unit configured for equating the pitch frequency histogram to be the first eigenfunction of the sum of coherent systems representation of a transformation cross coefficient; and
a third unit configured for solving an integral equation for the first eigenfunction of the transformation cross coefficient so as to define the optimal illumination for the full-chip layer.
22. The apparatus according to claim 21, wherein the first unit weights all pitches equally in the pitch frequency histogram.
23. The apparatus according to claim 21, wherein the third unit solves the integral equation for the first eigenfunction of the transformation cross coefficient such that the first eigenfunction becomes substantially identical to the pitch frequency.
24. The apparatus according to claim 23, wherein the third unit minimizes a difference between the pitch frequency and the first eigenfunction by using a merit function to solve the integral equation for the first eigenfunction of the transformation cross coefficient.
25. The apparatus according to claim 21, wherein the merit function is essentially the convolution of the first eigenfunction with the pitch frequency.
26. The apparatus according to claim 21, wherein the third unit solves the integral equation for the first eigenfunction of the transformation cross coefficient such that the first eigenfunction has a value of one for every non-zero value in the pitch frequency.
27. The apparatus according to claim 21, wherein the first unit obtains the pitch frequency by determining the separation between adjacent features on the full-chip layer that are within a coherence radius.
28. The apparatus according to claim 21, wherein the first unit obtains the pitch frequency by representing adjacent features on the full-chip layer with Dirac delta functions and measuring separation between the Dirac delta functions.
29. The apparatus according to claim 21, wherein the first unit obtains the pitch frequency for a random hole pattern or for a periodic hole pattern as a function of hole separation and as a function of angular separation.
30. The apparatus according to claim 21, further comprising:
a fourth unit configured for determining whether pitch frequencies fall into a negative region of the first eigenfunction by using the optimized illumination; and
a fifth unit for separating the pitch frequencies which fall into the negative region into another layer to be imaged with a second exposure, wherein
optimizing illumination for said another layer is performed by the first to third unit.
31. A device manufacturing method comprising the steps of:
(a) providing a substrate that is at least partially covered by a layer of radiation-sensitive material;
(b) providing a projection beam of radiation using an imaging system;
(c) using a pattern on a mask to endow the projection beam with a pattern in its cross-section;
(d) projecting the patterned beam of radiation onto a target portion of the layer of radiation-sensitive material,
wherein in step (b), providing said projection beam includes the steps of:
determining a pitch frequency of a full-chip layer, the pitch frequency indicating how often a pitch occurs in the full-chip layer so as to generate a pitch frequency histogram of the full-chip layer;
equating the pitch frequency histogram to be the first eigenfunction of the sum of coherent systems representation of a transformation cross coefficient; and
solving an integral equation for the first eigenfunction of the transformation cross coefficient so as to define the optimal illumination for the full-chip layer.