1. A method of engraving a label on a wafer comprising:
i) measuring a present energy level of a laser beam emitted from a laser diode, wherein the present energy level corresponds to a present output power of the laser diode;
ii) calculating a temperature compensation value;
iii) adjusting a temperature of the laser diode in relation to a reference temperature and the temperature compensation value;
iv) irradiating the wafer With the laser beam from the laser diode, wherein a energy level of the laser beam corresponds to a reference output power; and
v) repeating steps i) through iv).
2. The method of claim 1, wherein the reference temperature is about 25\xb0 C.
3. The method of claim 1, wherein calculating the temperature compensation value comprises:
calculating a present temperature of the laser diode in accordance with the present output power and an input current;
calculating a difference between the present temperature and the reference temperature of the laser diode; and
providing the difference as the temperature compensation value.
4. The method of claim 3, wherein calculating the present temperature of the laser diode comprises:
providing the input current and the present output power to a calculation program; and
calculating the present temperature using the calculation program.
5. The method of claim 1, wherein calculating the temperature compensation value comprises:
calculating a difference between the present output power and the reference output power, wherein the reference output power is the output power of the laser beam emitted from the laser diode at the reference temperature; and
calculating the temperature compensation value in accordance with the difference.
6. The method of claim 1, wherein adjusting the present temperature of the laser diode to the reference temperature comprises:
cooling or heating the laser diode in accordance with the temperature compensation value.
7. The method of claim 1, wherein repeating the steps i) through iv) comprises:
repeating the steps i) through iv) at predetermined intervals.
8. The method of claim 1, wherein repeating the steps i) through iv) comprises:
repeating the steps i) through iv) continuously.
9. An apparatus adapted to engrave a label on a wafer, comprising:
a light source member comprising a laser diode adapted to emit a laser beam;
a measuring member adapted to measure a present energy level of the laser beam, wherein the present energy level corresponds to a present output power;
a processing member adapted to compare the present energy level with a reference energy level to calculate a temperature compensation value for the laser diode, wherein the reference energy level is an energy level of the laser beam emitted from the laser diode at a reference temperature;
a heat-exchanging member adapted to adjust a temperature of the laser diode relative to the reference temperature and the temperature compensation value; and
a projection member adapted to project the laser beam onto the wafer.
10. The apparatus of claim 9, wherein the processing member comprises:
a memory module adapted to store an input current and a calculation program; and
a calculating module adapted to calculate the temperature compensation value in accordance with a difference between a present temperature of the laser diode and the reference temperature,
wherein the present temperature is calculated using the calculation program in relation to the input current and the present output power.
11. The apparatus of claim 10, wherein the reference temperature is about 25\xb0 C.
12. The apparatus of claim 9, wherein the light source member further comprises:
an internal power supply adapted to apply an operating voltage to the laser diode; and
a controller adapted to control an amount of current provided by the internal power supply to the laser diode.
13. The apparatus of claim 9, wherein the measuring member comprises a photometer adapted to collect a portion of the laser beam, to output a photocurrent corresponding to the present energy level of the laser beam, and to convert the photocurrent into a voltage.
14. The apparatus of claim 9, wherein the heat-exchanging member comprises a chiller and a heating pump positioned adjacent to the light source member.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1.-18. (canceled)
19. A thin layer semi-conductor structure including a semi-conductor surface layer separated from a support substrate by an intermediate zone, the intermediate zone being a multi-layer electrically insulating the semi-conductor surface layer from the support substrate, providing an electrical quality of interface with the semi-conductor surface layer and including a first layer providing the thermal conductivity between the semi-conductor surface layer and the support substrate, the intermediate zone including additionally a second layer located between the first layer and the support substrate, the second layer being of an electric insulating material, of low dielectric constant and providing bonding by molecular adhesion between the intermediate zone and the support substrate, the thickness of the first layer being chosen as a function of the dimension of the thermal dissipation zones of the electronic device or devices which are to be made from the semi-conductor surface layer.
20. A semi-conductor structure according to claim 19, wherein the second layer provides adhesion between the intermediate zone and the support substrate.
21. A semi-conductor structure according to claim 19, wherein the intermediate zone includes a third, electrical insulating, layer between the first layer and the semi-conductor surface layer, said third-layer providing to the intermediate zone said electrical quality of interface.
22. A semi-conductor structure according to claim 21, wherein, the semi-conductor structure being an SOI structure, the third layer is a layer of silicon oxide.
23. A semi-conductor structure according to claim 22, wherein the third layer is a layer of thermal silicon oxide.
24. A semi-conductor structure according to claim 19, the semiconductor structure being an SOI structure, wherein the second layer is a layer of silicon oxide.
25. A semi-conductor structure according to claim 19, wherein the first layer is constituted by a material chosen from among polycrystalline silicon, diamond, alumina, silicon nitride, aluminum nitride, boron nitride and silicon carbide.
26. A semi-conductor structure according to claim 19, wherein the first layer is in contact with the semi-conductor surface layer and provides said electrical quality of interface.
27. A semi-conductor structure according to claim 26, wherein the semi-conductor structure being an SOI structure, said first layer is a layer of cubic silicon carbide.
28. A process for manufacturing a semi-conductor structure according to claim 19, including the following stages:
manufacture of the layers of the intermediate zone on one face of a first substrate intended to supply said semi-conductor surface layer andor on one face of a second substrate intended to supply the support substrate of the structure,
bonding of the first substrate on the second substrate, said faces being placed opposite each other,
making of said semi-conductor surface layer.
29. A process according to claim 28, wherein making said semi-conductor surface layer includes reducing the thickness of the first substrate.
30. A process according to claim 28, wherein bonding the first substrate onto the second substrate is achieved by molecular adhesion.
31. A process according to claim 30, wherein the manufacturing stage of the layers of the intermediate zone includes the deposition of at least one bonding layer to allow bonding by molecular adhesion.
32. A process according to claim 31, wherein said bonding layer is a silicon oxide layer.
33. A process according to claim 28, wherein the first layer is a layer of a material chosen from among polycrystalline silicon deposited by LPCVD, diamond deposited by PECVD, alumina deposited by reactive cathode sputtering, silicon nitride deposited by CVD, aluminum nitride deposited by CVD, boron nitride deposited by CVD and silicon carbide deposited by CVD.
34. A process according to claim 29, wherein the reduction in the thickness of the first substrate is obtained by using one or more technologies from among: rectification, chemical etching, polishing, separation following thermal treatment along a cleavage plane induced by ion implantation.