I claim:
1. A method of inducing a specific protective immune response to the Human Immunodeficiency Virus in a human being, comprising the steps of:
isolating antigen-presenting dendritic cells from said human being, and pulsing said dendritic cells with synthetic peptides that bind said human being’s Class I Major Histocompatiblity types, said peptides corresponding to conserved structural and functional gene products of said Human Immunodeficiency Virus, and injecting said pulsed dendritic cells intravenously into said human being, and injecting said human being with substantially pure Chikungunya Virus.
2. The method of claim 1 wherein said substantially pure Chikungunya Virus is purified by passing said virus through living cells with an active transmembrane gradient; and passing said virus through subhuman primates to confirm the elimination of neurovirulence from the virus.
3. The method of claim 2 wherein said cells with an active transmembrane gradient are African Green Monkey Kidney Cells are infected with virus at less than 5 plaque-forming unitsml.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An electrical fuse circuit comprising:
a plurality of groups, each of the groups including:
a capacitor composing an electrical fuse;
a write circuit breaking an insulating film of said capacitor by applying a voltage across both terminals of said capacitor in accordance with one of a plurality of write signals; and
a precharge circuit precharging with respect to the terminal of said capacitor,
wherein the precharge circuit is coupled to a low-voltage-side terminal of the capacitor,
wherein each of the plurality of write signals is supplied to the corresponding write circuit of each of the plurality of groups at different timings with one another and during a period of time when a precharge operation is not being performed, and
wherein the precharge operation is performed during a period of time when the write signals are inactive.
2. The electrical fuse circuit according to claim 1
wherein said write circuits in the respective groups apply voltage to said capacitors in accordance with the write signal, respectively, at mutually different timings.
3. The electrical fuse circuit according to claim 1,
wherein, otherwise, said precharge circuit applies a precharge potential to a second terminal of said capacitor in accordance with a precharge signal to put the second terminal of said capacitor into a floating state.
4. A memory device comprising:
an electrical fuse circuit described in claim 1;
a normal memory cell array including a plurality of memory cells; and
a redundant memory cell array including a memory cell to replace the memory cell in said normal cell array;
wherein a capacitor in said electrical fuse circuit memorizes an address of the memory cell in said normal memory cell array to be replaced.
5. The electrical fuse circuit according to claim 2,
wherein the precharge operation is performed to the terminal of said capacitor during a period of time when said write circuits in the respective groups apply voltage to said capacitors in accordance with the write signal, respectively, at mutually different timings.
6. The electrical fuse circuit according to claim 3,
wherein said precharge circuit includes a first field-effect transistor connected to the terminal of said capacitor with a drain thereof and connected to the precharge potential with a source thereof.
7. The electrical fuse circuit according to claim 3,
wherein said write circuit breaks the insulating film of said capacitor by applies a first potential to a first terminal of said capacitor and applying a second potential having a lower potential than that of the first potential to a second terminal of said capacitor, in accordance with the write signal.
8. The electrical fuse circuit according to claim 3, further comprising a second field-effect transistor connected to between the drain of the first field-effect transistor and the second terminal of said capacitor.
9. The electrical fuse circuit according to claim 6, further comprising a second field-effect transistor connected to between the drain of the first field-effect transistor and the terminal of said capacitor.
10. The electrical fuse circuit according to claim 7,
wherein, otherwise, said write circuit applies the second potential to the second terminal of said capacitor in accordance with the write sign alto put the second terminal of said capacitor into a floating state.
11. The electrical fuse circuit according to claim 10,
wherein said write circuit includes a first field-effect transistor connected to the write signal with a gate thereof and connected to a second terminal of said capacitor with a source thereof.
12. The electrical fuse circuit according to claim 8,
wherein said precharge circuit includes a third field-effect transistor connected to the second terminal of said capacitor via said second field-effect transistor with a drain thereof and to a precharge potential with a source thereof.
13. An electronic part comprising a memory device described in claim 4, said memory device including an electrical fuse circuit, a normal memory cell array and a redundant memory cell array and a semiconductor memory chip provided with the electrical fuse circuit, the normal memory cell array and the redundant memory cell array therein,
wherein the semiconductor memory chip is mounted in a package.
14. The electronic part according to claim 13,
wherein a chip having a memory controller controlling an operation of a write circuit with respect to the semiconductor memory chip is mounted in the same package as of said semiconductor memory device.