1. A reconfigurable logic cell comprising n inputs (A,B, . . . ), n being greater than or equal to 2, and capable of producing at least four logic functions with which logic signals provided on the n inputs (A,B, . . . ) may be processed, characterized in that it comprises, between the ground and the output (F) of the cell, at least one first branch including n dual gate N type MOSFET transistors (M1,M2, . . . ) in series and n\u22121 branches in parallel with the first branch, each provided with one dual gate N type MOSFET transistor (M3), each of the logic functions corresponding to a given configuration of the cell wherein a specific set of control signals (C1,C2, . . . ) is applied on the rear gates of at least one portion of the transistors (M2,M3, . . . ), each control signal (C1,C2, . . . ) being capable of setting the transistor (M2,M3, . . . ) to a particular operating mode, the n inputs (A,B, . . . ) being each connected on the front gate of one of the n transistors (M1,M2, . . . ) of the first branch, n\u22121 inputs (B) being also applied on the front gate of one (M3) of the n\u22121 transistors of the n\u22121 branches in parallel with the first branch.
2. The reconfigurable cell according to claim 1, characterized in that n is equal to 2, a first input (A) being connected to the connected gates of a first transistor (M1) of the first branch, a second input (B) being connected to the front gate of the second transistor (M2) of the first branch, the gates of which are separate, and to the front gate of the transistor (M3) of the second branch, the gates of which are also separate; control signals (C1,C2) applied on the rear gates of the second transistor (M2) of the first branch and of the transistor (M3) of the second branch enabling the reconfigurable cell to be made capable of performing four functions.
3. The reconfigurable cell according to claim 1, characterized in that n is equal to 2, all the transistors being with separate gates, a first input (A) being connected to the front gate of a first transistor (M1) of the first branch, a second input (B) being connected to the front gate of a second transistor (M2) of the first branch and to the front gate of the transistor of the second branch (M4), a third input (C) being connected to the front gate of the third transistor (M3) of the first branch and to the front gate of the transistor (M5) of the third branch, five control signals (C1 to C5) applied on the rear gates of the five transistors (M1 to M5) enables the reconfigurable cell to be made capable of performing eleven functions.
4. The reconfigurable cell according to claim 1, characterized in that the control signals (C1,C2, . . . ) have a voltage selected from \u2212Vdd, 0, +Vdd, Vdd being the power supply voltage of the cell.
5. The reconfigurable cell according to claim 1, characterized in that it is implemented in dynamic logic, the branches of the cell being placed in series, between the ground and a power supply terminal, between a preload transistor of the P type (Mp) and an evaluation transistor of the N type (Mn), the gates of which are controlled by a clock signal and in that the transistors (M3,M4 and M5) of the n\u22121 branches in parallel with the first branch are asymmetrical.
6. The reconfigurable cell according to claim 5, characterized in that all the transistors are asymmetrical.
7. The reconfigurable cell according to claim 1, characterized in that it is implemented in static logic, the branches of the cell being placed in series between the ground and a power supply terminal (Vdd) with a complementary network of transistors placed between the point common to the branches of the cell, the most distant from the ground, forming the output (F) of the cell, and the power supply terminal (Vdd).
8. The reconfigurable cell according to claim 7, characterized in that n is equal to 2, and the complementary network comprises, between the power supply terminal and the output (F) of the cell, a P type MOSFET transistor (Q6) in series with two P type MOSFET transistors (Q4,Q5) placed in parallel with each other and both connected to the output (F) of the cell, the first input (A) being connected to the connected gates of a first P type transistor (Q5) placed in parallel, the second input (B) being connected to the front gate of the second P type transistor (Q4) placed in parallel, the gates of which are separate, and to the front gate of the P type transistor (Q6) placed in series, the gates of which are also separate; two control signals (C3,C4) applied on the rear gates of the second P type transistor (Q4) placed in parallel and of the P type transistor (Q6) placed in series enabling the reconfigurable cell to be made capable of performing four functions.
9. The reconfigurable cell according to claim 8, characterized in that as the transistors are all symmetrical, the WL ratio of the P type transistor (Q4) with separate gates placed in parallel is adjusted so as to allow blocking of this transistor when a voltage Vdd is applied on its rear gate.
10. The reconfigurable cell according to claim 8, characterized in that the P type transistor (Q4) with separate gates placed in parallel is asymmetrical.
11. The reconfigurable cell according to claim 10, characterized in that all the transistors are asymmetrical.
12. The reconfigurable cell according to claim 5, characterized in that the asymmetry of the transistors is such that it allows increase in the threshold voltage of the front gate, controlled by the input logic signal, relatively to that of the rear gate, controlled by the control signal of the logic function of the cell.
13. The reconfigurable cell according to claim 5, characterized in that the asymmetry of the transistor(s) is selected so as to ensure a compromise between the stability of the operating modes of the transistor(s) and the functions produced by the cell with bias voltages below the gate breakdown limit of the transistor(s).
14. The reconfigurable cell according to claim 1, characterized in that the asymmetrical gates have different gate oxide thicknesses.
15. The reconfigurable cell according to claim 1, characterized in that the asymmetrical gates are such that they have asymmetrical work functions.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor assembly, comprising:
a semiconductor die having a plurality of bond-sites;
a dielectric support layer having a first side and a second side, wherein the die is attached to the second side of the support layer, wherein the support layer is a photoimageable polymer;
a plurality of preformed conductive interconnects, wherein individual interconnects have a first portion in the support layer and a second portion spaced apart from the support layer; and
a dielectric encapsulant between the interconnects and around at least a portion of the die.
2. The assembly of claim 1 wherein the support layer is a polymer that adheres to the die.
3. The assembly of claim 1 wherein the interconnects are arranged in a predetermined pattern outside of a footprint of the die, and the dielectric encapsulant is in a flowable state.
4. The assembly of claim 1 wherein the die has a first height and the interconnects have a second height greater than the first height.
5. The assembly of claim 1 wherein the interconnects comprise a plurality of preformed pins, and wherein the first portions of the pins have a beveled portion.
6. The assembly of claim 1, further comprising at least a portion of a plate at least partially surrounding the support layer.
7. The assembly of claim 1 wherein the semiconductor assembly is a first semiconductor assembly and wherein a second semiconductor assembly generally similar to the first semiconductor assembly is stacked on the first semiconductor assembly, the second semiconductor comprising:
a semiconductor die having a plurality of bond-sites;
a dielectric support layer having a first side and a second side, wherein the die is attached to the second side of the support layer;
a plurality of preformed conductive interconnects, wherein individual interconnects have a first portion in the support layer and a second portion spaced apart from the support layer; and
a dielectric encapsulant between the interconnects and around at least a portion of the die.
8. A plurality of through package interconnects in a semiconductor assembly including a die, a dielectric support layer, and an encapsulant, the interconnects comprising:
a plurality of preformed electrically conductive pins projecting from the support layer in a predetermined array outside of a footprint of the die, wherein the pins are arranged in the predetermined array apart from the encapsulant, and wherein the individual pins have a beveled end portion embedded in the support layer.
9. An intermediate article of manufacture of a semiconductor assembly, comprising:
a dielectric support layer;
a plurality of semiconductor dies attached to the support layer such that individual dies are at die sites across the support layer;
a plurality of preformed conductive pins having first portions retained in the support layer and second portions projecting from the support layer, wherein the pins are arranged in a plurality of discrete pin arrays, and wherein the second portions of the pins are free-standing without a solid material therebetween; and
a plate having a cavity, wherein the support layer is formed in the cavity and the pins are mounted to and project from the plate.
10. The article of claim 9 wherein the plate is configured to be removable from the article.
11. The article of claim 10 wherein the plate is made from a curable epoxy.
12. The article of claim 9 wherein each of the preformed conductive pins has a generally cylindrical shape.
13. The article of claim 12 wherein each of the preformed conductive pins has a diameter of at least approximately 100 \u03bcm.
14. The article of claim 9 wherein the dies extend a first height from the support layer and the preformed conductive pins extend a second height from the support layer, and wherein the second height is greater than the first height.
15. The article of claim 9 wherein each of the preformed conductive pins has a beveled end portion at least partially embedded in the support layer.
16. A system, comprising:
at least one of a processor, a memory device and an input or output device, wherein at least one of the processor, memory device and input or output device includes a semiconductor assembly comprising\u2014
a die having a plurality of bond-sites;
a dielectric support layer, wherein the die is attached to the support layer;
a plurality of preformed conductive interconnects projecting from the support layer, wherein individual interconnects have a first portion in the support layer; and
a dielectric encapsulant molded between the interconnects and around at least a portion of the die, wherein the dielectric encapsulant contacts an outer surface of the corresponding interconnects.
17. The system of claim 16 wherein the plurality of preformed conductive interconnects comprises a plurality of preformed pins, and wherein the first portions of the preformed pins are at least partially embedded in the support layer.
18. The system of claim 16 wherein the support layer retains the interconnects in a predetermined array around the die.