1. A computer-accessible storage medium having program instructions stored therein that, in response to execution by a computer system, cause the computer system to perform operations including:
generating a statistical distribution of a first design parameter of a memory circuit;
generating a statistical distribution of a second design parameter of the memory circuit;
determining a first probability density function of the statistical distribution of the first design parameter;
determining a second probability density function of the statistical distribution of the second design parameter;
combining the first probability density function and the second probability density function to form a composite probability density function;
calculating a probability, dependent upon the composite probability density function, of a performance parameter of the memory circuit achieving a pre-determined performance value; and
optimizing a third design parameter of the memory circuit such that the probability is equal to a pre-determined goal.
2. The computer-accessible storage medium of claim 1, wherein generating the statistical distribution of the first design parameter or the second design parameter comprises running a Monte Carlo circuit simulation.
3. The computer-accessible storage medium of claim 1, wherein determining the first probability density function or the second probability density function comprises performing a curve fit.
4. The computer-accessible storage medium of claim 1, wherein combining the first probability density function and the second probability density function comprises multiplying the first probability density function and the second probability density function.
5. The computer-accessible storage medium of claim 1, wherein calculating the probability comprises numerically integrating the composite probability density function.
6. A method comprising:
performing by one or more computers:
determining a first probability density function corresponding to a statistical variation of a first design parameter of a circuit;
determining a second probability density function corresponding to a statistical variation of a second design parameter of the circuit;
combining the first probability density function and the second probability density function into a composite probability density function; and
optimizing a third design parameter of the circuit dependent upon the composite probability density function.
7. The method of claim 6, wherein the circuit comprises a memory circuit.
8. The method of claim 7, wherein the first design parameter comprises a bit line differential voltage, wherein the second design parameter comprises a minimum sense amplifier differential voltage, and wherein the third design parameter comprises a bit line development time.
9. The method of claim 7, wherein the first probability density function corresponds to a normally distributed probability density function.
10. The method of claim 7, wherein the second probability density function corresponds to an extreme value probability density function.
11. A system comprising:
one or more memories that, during operation, store instructions, and
one or more processors that, during operation, receive instructions from the one or more memories and execute the instructions to cause the system to perform operations comprising:
generating a first statistical distribution of the operation of a first part of a circuit;
generating a second statistical distribution of the operation of a second part of the circuit; and
optimizing a third part of the circuit dependent upon the first statistical distribution and the second statistical distribution.
12. The system of claim 11, wherein the first part of the circuit comprises a bit line of a memory circuit, wherein the second part of the circuit comprises a sense amplifier of the memory circuit, and wherein the third part of the circuit comprises a timing and control unit of the memory circuit.
13. The system of claim 12, wherein optimizing the third part of the circuit comprises one or more of: generating a first probability density function dependent upon the first statistical distribution, or generating a second probability density function dependent upon the second statistical distribution.
14. The system of claim 13, wherein optimizing the third part of the circuit further comprises multiplying the first probability density function by the second probability density function.
15. The system of claim 14, wherein optimizing the third part of the circuit further comprises modifying a development time dependent upon the product of the first probability density function and the second probability density function.
16. A computer-accessible storage medium having program instructions stored therein that, in response to execution by a computer system, cause the computer system to perform operations including:
generating a distribution of a minimum sense amplifier input signal voltage of a memory circuit;
generating a distribution of a bit line output signal voltage of the memory circuit;
converting the distribution of the minimum sense amplifier input signal voltage to a sense amplifier probability density function;
converting the distribution of the bit line output signal voltage to a bit line probability density function;
combining the sense amplifier probability density function and the bit line probability density function into a composite probability density function;
calculating, dependent upon the composite probability density function, a probability of a misread; and
optimizing a bit line output signal voltage development time such that the probability of a misread achieves a pre-determined probability goal.
17. The computer-accessible storage medium of claim 16, wherein calculating the probability of a misread comprises calculating a probability of the bit line output signal voltage achieving an output voltage.
18. The computer-accessible storage medium of claim 17, wherein calculating the probability of a misread further comprises, calculating a probability of the minimum sense amplifier input voltage matching the output voltage.
19. The computer-accessible storage medium of claim 18, wherein calculating the probability of a misread further comprises multiplying the probability of the bit line output signal voltage achieving an output voltage by the probability of the minimum sense amplifier input voltage matching the output voltage.
20. The computer-accessible storage medium of claim 19, wherein the probability of a misread is dependent upon a number of sense amplifiers included in the memory circuit.
21. A method comprising:
performing by one or more computers:
simulating a sense amplifier of a memory circuit to generate a statistical data of the minimum input voltage of the sense amplifier;
simulating a data storage cell of the memory circuit to generate a statistical data of the output voltage of the data storage cell;
determining a sense amplifier probability density function based in part upon the statistical data of the minimum input voltage of the sense amplifier;
determining a data storage cell probability density function based in part upon the statistical data of the output voltage of the data storage cell; and
calculating a probability of a read failure based in part upon the sense amplifier probability density function and the data storage cell probability density function.
22. The method of claim 21, wherein determining the sense amplifier probability density function comprises curve fitting the statistical data of the minimum input voltage of the sense amplifier.
23. The method of claim 22, wherein the sense amplifier probability density function is dependent upon one or more of a number of sense amplifiers or a number of redundant sense amplifiers.
24. The method of claim 21, wherein determining the data storage cell probability density function comprises curve fitting the statistical data of the output voltage of the data storage cell.
25. The method of claim 24, wherein the data storage cell probability density function is dependent upon one or more of a number of data storage cells or a number of redundant data storage cells.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A clock generation apparatus comprising:
AD conversion means for converting an input analog signal into a digital signal;
arithmetic means for generating a threshold used as a reference when binarizing the digital signal to generate a binary signal and a synchronous clock for sampling the binary signal, on the basis of the digital signal;
binarization means for comparing the digital signal with the threshold generated by the arithmetic means, and outputting a result of the comparison as the binary signal; and
latch means for latching the binary signal with the synchronous clock and outputting a synchronous signal, wherein
the arithmetic means comprises:
threshold detection means for detecting a maximum value and a minimum value of the digital signal in a predetermined period, and outputting an average of the maximum value and the minimum value as the threshold;
rise time detection means for detecting a rise time as a time of intersection of the threshold and a line connecting two values of the digital signal, one of the two values being lower that the threshold and another of the two values being higher than the threshold, when the digital signal changes from the lower value to the higher value;
fall time detection means for detecting a fall time as a time of intersection of the threshold and a line connecting two values of the digital signal, one of the two values being higher than the threshold and another of the two values being lower than the threshold, when the digital signal changes from the higher value to the lower value;
input rate detection means for obtaining time intervals between adjacent rise and fall times during a predetermined period, and outputting a minimum value of the time intervals as an input rate of the input analog signal; and
synchronous clock output means for obtaining a half timing of the input rate after an edge of the input analog signal is detected on the basis of the input rate and the rise and fall times and outputting a first one of the synchronous clock at that timing, and obtaining a timing of the input rate after the first synchronous clock is output and outputting a second or later one of the synchronous clock at that timing.
2. A clock generation apparatus comprising:
AD conversion means for converting an input analog signal into a digital signal;
arithmetic means for generating a threshold used as a reference when binarizing the digital signal to generate a binary signal and a synchronous clock for sampling the binary signal, on the basis of the digital signal;
binarization means for comparing the digital signal with the threshold generated by the arithmetic means, and outputting a result of the comparison as the binary signal; and
latch means for latching the binary signal with the synchronous clock and outputting a synchronous signal; wherein
the arithmetic means comprises:
threshold detection means for detecting integrals of the digital signal in a predetermined period, and outputting an average of the integrals as the threshold;
rise time detection means for detecting a rise time as a time of intersection of the threshold and a line connecting two values of the digital signal, one of the two values being lower than the threshold and another of the two values being higher than the threshold, when the digital signal changes from the lower value to the higher value;
fall time detection means for detecting a fall time as a time of intersection of the threshold and a line connecting two values of the digital signal, one of the two values being higher than the threshold and another of the two values being lower than the threshold, when the digital signal changes from the higher value to the lower value;
input rate detection means for obtaining time intervals between adjacent rise and fall times during a predetermined period, and outputting a minimum value of the time intervals as an input rate of the input analog signal; and
synchronous clock output means for obtaining a half timing of the input rate after an edge of the input analog signal is detected on the basis of the input rate and the rise and fall times and outputting a first one of the synchronous clock at that timing, and obtaining a timing of the input rate after the first synchronous clock is output and outputting a second or later one of the synchronous clock at that timing.
3. The clock generation apparatus of claim 1, further comprising:
an oversampling digital filter for interpolating adjacent digital signals.
4. The clock generation apparatus of claim 2, further comprising:
an oversampling digital filter for interpolating adjacent digital signals.