1. A semiconductor device comprising:
lower electrodes on a substrate, each of the lower electrodes having a taller side with a height that is greater than an opposing shorter side;
a supporting layer pattern disposed between the lower electrodes to support the lower electrodes, the supporting layer pattern contacting the taller sides of the lower electrodes;
a dielectric layer disposed on the lower electrodes and the supporting layer pattern;
an upper electrode disposed on the dielectric layer;
an inter-metal dielectric layer disposed on the upper electrode; and
a metal contact penetrating through the inter-metal dielectric layer and contacting with the upper electrode, a bottom portion of the metal contact being aligned above the shorter sides of the lower electrodes.
2. The semiconductor device of claim 1, further comprising:
a conductive line on the substrate, the conductive line contacting a bottom portion of the lower electrodes.
3. The semiconductor device of claim 1, wherein an upper surface of the shorter side of a lower electrode aligned with the bottom portion of the metal contact is lower than a bottom portion of the supporting layer pattern.
4. The semiconductor device of claim 1, wherein the supporting layer pattern has a pattern shape including a hole, and the metal contact is aligned with an inner portion of the hole.
5. The semiconductor device of claim 1, wherein the supporting layer pattern has a line shape, and the metal contact is aligned with an inner portion of a gap between adjacent supporting layer patterns.
6. The semiconductor device of claim 1, wherein the lower electrodes, the dielectric layer, the upper electrode, and the supporting layer pattern constitute at least one capacitor, the at least one capacitor including a peripheral capacitor in a peripheral region of the substrate.
7. The semiconductor device of claim 6, wherein the at least one capacitor includes a cell capacitor in a cell region of the substrate.
8. The semiconductor device of claim 1, wherein the lower electrode or the supporting layer pattern is overlapped by the metal contact.
9. A semiconductor device comprising:
lower electrodes on a substrate, each of the lower electrodes having a taller side that tapers down to an opposing shorter side, at least two of the lower electrodes have shorter sides facing each other;
a supporting layer pattern disposed between the taller sides of the lower electrodes and configured to support the lower electrodes;
a dielectric layer disposed on the lower electrodes and the supporting layer pattern;
an upper electrode disposed on the dielectric layer;
an inter-metal dielectric layer disposed on the upper electrode; and
a metal contact penetrating through the inter-metal dielectric layer and contacting with the upper electrode, a bottom portion of the metal contact being aligned above and between the shorter sides of the lower electrodes.
10. The semiconductor device of claim 9, wherein the lower electrodes are arranged about a common center, the shorter sides of the lower electrodes being closer to the common center than the taller sides.
11. The semiconductor device of claim 9, wherein the lower electrodes are arranged in rows such that the shorter sides of at least two adjacent rows of lower electrodes face each other.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
We claim:
1. A fusible link configuration in or on integrated circuits, comprising:
a memory field segment;
at least one bank of fusible links defining a total number of said fusible links and configured beside and associated with said memory field segment, said at least one bank of said fusible links divided into units of said fusible links, each one of said units of said fusible links including a smaller number of said fusible links than said total number of said fusible links, said units of said fusible links being grouped to define a width of said at least one bank of said fusible links and being grouped such that at least some of said fusible links are disposed adjacently in a direction that is transverse with respect to a direction of said width of said at least one bank of said fusible links; and
an evaluation logic unit electrically connected to said fusible links for determining whether one or more of said fusible links is severed.
2. The fusible link configuration according to claim 1, wherein said at least one bank of said fusible links is divided into two halves of said fusible links that are disposed beside each other at right angles with respect to the direction of said width of said at least one bank of said fusible links, and said width of said at least one bank of said fusible links is one half of a width that it would have if it were not divided into said two halves.
3. The fusible link configuration according to claim 1, comprising:
a ground track;
said at least one bank of said fusible links divided into a first half of said fusible links and a second half of said fusible links;
said first half of said fusible links having first ends individually wired to said evaluation logic unit and having second ends connected to said ground track;
said second half of said fusible links having first ends individually wired to said evaluation logic unit and having second ends connected to said ground track; and
said second ends of said fusible links of said first half disposed to adjoin said second ends of said fusible links of said second half in the direction that is transverse with respect to the direction of said width of said at least one bank of said fusible links.
4. The fusible link configuration according to claim 3, comprising wiring, connecting said fusible links to said evaluation logic unit, that is routed in at least one metallization plane of a chip.
5. In combination with a highly integrated memory chip, a fusible link configuration, comprising:
a memory field segment;
at least one bank of fusible links defining a total number of said fusible links and configured beside and associated with said memory field segment, said at least one bank of said fusible links divided into units of said fusible links, each one of said units of said fusible links including a smaller number of said fusible links than said total number of said fusible links, said units of said fusible links being grouped to define a width of said at least one bank of said fusible links and being grouped such that at least some of said fusible links are disposed adjacently in a direction that is transverse with respect to a direction of said width of said at least one bank of said fusible links; and
an evaluation logic unit electrically connected to said fusible links for determining whether one or more of said fusible links is severed.