1. A track assembly for a machine comprising:
a first chain assembly:
a track pin;
a second chain assembly wherein the track pin couples the second chain assembly with the first chain assembly, the first and second chain assemblies each including an inner track link and an outer track link, wherein the inner track link includes a shoulder;
a rotatable bushing positioned about the track pin;
a sleeve bearing disposed within a first bore of the inner track link and positioned about the track pin, wherein the sleeve bearing is disposed to transfer axial loads to the shoulder;
a first seal member disposed between the inner track link and the rotatable bushing;
a second seal member disposed between the inner and outer track links;
a first thrust ring positioned about the track pin and engaged with the rotatable bushing;
a second thrust ring disposed about the track pin and engaged with the sleeve bearing; and
a first contact member engaged with the first seal member and a second contact member fastened to either the inner track link or the outer track link and engaged with the second seal member, the first and second contact members configured to inhibit wear of the first and second seal members.
2. The track assembly of claim 1, wherein the first and second contact members are formed of corrosion and abrasion resistant material.
3. The track assembly of claim 1, wherein the first contact member is fastened to an end face of the rotatable bushing.
4. The track assembly of claim 1, wherein the second contact member is fastened to the inner track link.
5. The track assembly of claim 1, wherein the second contact member is fastened to the outer track link.
6. The track assembly of claim 1, wherein the second seal member is disposed within the first bore of the inner track link.
7. The track assembly of claim 1, wherein the second seal member is disposed within a bore of the outer track link.
8. The track assembly of claim 1, wherein the first seal member is disposed within a second bore of the inner track link, the second bore axially aligned with the first bore.
9. The track assembly of claim 1, wherein the first thrust ring is configured to push against the end face of the rotatable bushing and the second thrust ring is configured to push against an end face of the sleeve bearing.
10. A method of protecting components of a machine track assembly during operation, the machine track assembly including an outer track link, an inner track link, a track pin, a rotatable bushing positioned about the track pin, a first seal member disposed between the inner track link and the rotatable bushing, and a second seal member disposed between the inner and outer track links, wherein the inner track link includes a shoulder, the method comprising:
disposing a sleeve bearing about the track pin, wherein the sleeve bearing is disposed to transfer axial loads to the shoulder; and
protecting the first and second seal members at least in part by:
assembling a first thrust ring about the track pin and engaging the first thrust ring with the rotatable bushing;
assembling a second thrust ring about the track pin and engaging the second thrust ring with the sleeve bearing;
engaging a first contact member with the first seal member;
fastening a second contact member to the inner track link or the outer track link; and
engaging the second contact member with the second seal member.
11. The method of claim 10, wherein disposing the sleeve bearing about the track pin further includes inserting the sleeve bearing within a first bore of the inner track link.
12. The method of claim 10, wherein engaging a first contact member with the first seal member includes fastening the first contact member to an end face of the rotatable bushing.
13. The method of claim 10, wherein engaging a second contact member with the second seal member includes fastening the second contact member to the inner track link.
14. The method of claim 10, wherein engaging a second contact member with the second seal member includes fastening the second contact member to the outer track link.
15. A track-type machine comprising:
a frame; and
a track mounted on the frame, the track including a first chain assembly;
a plurality of track pins;
a second chain assembly, wherein the plurality of track pins couple the first chain assembly with the second chain assembly, the first and second chain assemblies including a plurality of inner track links and a plurality of outer track links, wherein the inner track links each include a shoulder;
a rotatable bushing positioned about each track pin;
a sleeve bearing disposed within a first bore of each inner track link and positioned about each track pin, wherein the sleeve bearing is disposed to transfer axial loads to the shoulder;
a first seal member disposed between each inner track link and the rotatable bushing;
a second seal member disposed between each inner and outer track link;
a first thrust ring positioned about each track pin and engaged with the rotatable bushing;
a second thrust ring disposed about each track pin and engaged with the sleeve bearing; and
a first contact member engaged with the first seal member and a second contact member engaged with the second seal member, the first and second contact members configured to inhibit wear of the first and second seal members;
wherein the first seal member is coupled to a bore of the inner track link and the second seal member is coupled to a bore of the inner track link.
16. The track-type machine of claim 15, wherein the first contact member is fastened to an end face of the rotatable bushing.
17. The track-type machine of claim 15, wherein the second contact member is fastened to each outer track link.
18. The track-type machine of claim 15, wherein the first thrust ring is configured to push against the end face of the rotatable bushing and the second thrust ring is configured to push against an end face of the sleeve bearing.
19. The track assembly of claim 15, wherein the outer track link is positioned about a collar fastened to the track pin, and the second contact member is fastened to the collar.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. In a signal processing device, a method for serially calculating a Fast Hadamard Transform of size N of a first order of a sampled signal from a first channel, the method comprising:
serially storing a plurality of sampled Hadamard Transform signals of a size M of a second order, the size M of the second order being less than the size N of the first order;
computing a sum of two computations from a first sampled Hadamard Transform signal of size M and a second sampled Hadamard Transform signal from the plurality of sampled Hadamard Transform signals of the second order;
storing the sum;
computing a difference of two computations from the first sampled Hadamard Transform signal of size M and the second sampled Hadamard Transform signal from the plurality of sampled Hadamard Transform signals of the second order;
storing the difference; and
combing the sum and the difference to form a sampled Hadamard Transform signal of size N of the sampled signal from the first channel,
wherein the sampled signal from the first channel is representative of a wireless communication transmitted to the signal processing device.
2. The method of claim 1, wherein the sampled signal contains 2N samples where N is an integer.
3. The method of claim 1, wherein the sum of computations from the first sampled Hadamard Transform signal of the second order and of the second sampled Hadamard Transform signal of the second order is computed during the same clock cycle and the difference of computations from the first sampled Hadamard Transform signal of the second order and the second sampled Hadamard Transform signal of the second order is computed during a second clock cycle.
4. The method of claim 1, wherein the sum of computations from the first sampled Hadamard Transform signal of the second order and of the second sampled Hadamard Transform signal of the second order is computed during the same clock cycle and the difference of computations from the first sampled Hadamard Transform signal of the second order and the second sampled Hadamard Transform signal of the second order is computed during the same clock cycle.
5. The method of claim 1, wherein the size N of the first order is of the form 2K and the size M of the second order is of the form 2J, wherein K is greater than J.
6. The method of claim 1, wherein computing the difference of computations from the first sampled Hadamard Transform signal of the second order and the second sampled Hadamard Transform signal of the second order comprises the step of
computing a sum of the first sampled Hadamard Transform signal of the second order and a two’s complement of the second sampled Hadamard Transform signal of the second order.
7. The method of claim 1, wherein sampled Hadamard Transform signals of size order one (N=1) are samples from the sampled signal.
8. The method of claim 1, wherein the sampled Hadamard Transform signals of the second order are serially calculated using a method comprising the steps of:
serially storing a plurality of sampled Hadamard Transform signals of a third order, the third order being less than the second order;
computing a sum of a first sampled Hadamard Transform signal and a second sampled Hadamard Transform signal from the plurality of sampled Hadamard Transform signals of the third order;
storing the sum;
computing a difference of the first sampled Hadamard Transform signal and the second sampled Hadamard Transform signal from the plurality of sampled Hadamard Transform signals of the third order; and
storing the difference.
9. The method of claim 8, wherein computing a difference of the first sampled Hadamard Transform signal of the third order and the second sampled Hadamard Transform signal the third order comprises the step of computing a sum of the first sampled Hadamard Transform signal of the third order and a two’s complement of the second sampled Hadamard Transform signal of the third order.
10. The method of claim 8, wherein sampled Hadamard Transform signals of order one (1) are samples from the sampled signal.
11. The method of claim 8, wherein the sampled signal contains 2N samples where N is an integer.
12. The method of claim 8, wherein the sum of the first sampled Hadamard Transform signal of the third order and the second sampled Hadamard Transform signal of the third order is computed during a first clock cycle and the difference of the first sampled Hadamard Transform signal of the third order and the second sampled Hadamard Transform signal of the third order is computed during a second clock cycle.
13. The method of claim 8, wherein the sum of the first sampled Hadamard Transform signal of the third order and the second sampled Hadamard Transform signal of the third order is computed during the same clock cycle and the difference of the first sampled Hadamard Transform signal of the third order and the second sampled Hadamard Transform signal of the third order is computed during the same clock cycle.
14. The method of claim 8, wherein the first order is of the form 2K and the second order is of the form 2J and the third order is of the form 2I, wherein K is greater than J which is greater than I.
15. The method of claim 1, wherein the steps of computing and storing sums and differences are applied repeatedly to produce sampled Fast Hadamard Transform signals of successively greater size order.
16. The method of claim 15, wherein the steps of computing and storing sums and differences are first applied to samples of the sampled signal.
17. The method of claim 1, wherein each of the sampled Hadamard Transform signals is bit-reverse-ordered to produce a transformation of the sampled Hadamard Transform signal.
18. The method of claim 17, wherein all terms of each of the transformations of the sampled Hadamard Transform signals have a one to one correspondence to terms of the sampled Hadamard Transform signals.
19. The method of claim 17, wherein all rows of each of the transformations of the sampled Hadamard Transform signals have a one-to-one correspondence to rows of sampled Hadamard Transform signals.
20. The method of claim 1, wherein the size N is of the form 2K and the size M is of the form 2J, wherein K=1 and J=0.
21. The method of claim 1, wherein the size N is of the form 2K and the size M is of the form 2J, wherein K=2 and J=1.
22. An apparatus for serially calculating a Fast Hadamard Transform of a sampled signal from a first channel, comprising:
a first shift register for serially receiving samples of the signal;
a first two’s complement generator for producing a two’s complement of a first sample of the signal;
a first multiplexer for selecting between a first sample of the signal and the two’s complement of the signal to produce a multiplexer output; and
a first adder for generating a sum of a second sample of the signal and the multiplexer output.
23. The apparatus of claim 22, wherein the sampled signal contains 2N samples where N is an integer.
24. The apparatus of claim 22, wherein the first adder generates a sum of a first sample of the signal and the second sample of a signal during a first clock cycle and wherein the first adder generates a difference of a first sample of the signal and the second sample of the signal during a second clock cycle.
25. The apparatus of claim 22, wherein the first adder generates a sum of a first sample of the signal and the second sample of a signal during the same clock cycle and wherein the first adder generates a difference of a first sample of the signal and the second sample of the signal during the same clock cycle.
26. The apparatus of claim 25, wherein the sum and the difference are passed to a second shift register.
27. The apparatus of claim 22, wherein the first shift register is a random access memory.
28. The apparatus of claim 22, wherein the first shift register is a FIFO.
29. The apparatus of claim 22, wherein the first adder is shared with a second channel.
30. The apparatus of claim 22 further comprising:
a second shift register for serially receiving the sum from the first adder;
a second two’s complement generator for producing a two’s complement of a signal stored in the second shift register;
a second multiplexer for selecting between a signal stored in the second shift register and the two’s complement of said signal to produce a multiplexer output; and
a second adder for generating a sum of another signal stored in the second shift register and the multiplexer output.
31. In a signal processing device, a method for serially calculating a Fast Hadamard Transform of a sampled signal from a first channel, the method comprising:
serially storing samples of the signal;
computing a first sum of a first sample of the signal and a last sample of the signal;
storing the first sum;
computing a second sum of a first sample of the signal and a two’s complement of the last sample of the signal;
storing the second sum; and
combining the first sum and the second sum to form a sampled Hadamard Transform signal of size N of the sampled signal from the first channel,
wherein the sampled signal from the first channel is representative of a wireless communication transmitted to the signal processing device.
32. An apparatus for serially calculating a Fast Hadamard Transform of order size 2N of a sampled signal from a first channel, comprising:
a first shift register for serially receiving computations from Hadamard Transforms of order size 2N-1;
a first two’s complement generator for producing a two’s complement of a first computation from a first Hadamard Transform of order size 2N-1 that is stored in the first shift register; and
a first adder for generating a sum of a second computation from a Hadamard Transform of order size 2N-1 and the first Hadamard Transform of the order size 2N-1, the first adder also generating a sum of the second computation of the Hadamard Transform of order size 2N-1 and a two’s complements of the first computation of a Hadamard Transform of order size 2N-1.
33. The apparatus of claim 32, further comprising a first multiplexer for selecting between the first Hadamard Transform of order size 2N-1 and the two’s complements of the first Hadamard Transform of the order size 2N.
34. The apparatus of claim 32, further comprising a second shift register for serially receiving Hadamard Transforms of order size 2N.
35. The apparatus of claim 32, wherein the sampled signal contains 2N samples where N is an integer.
36. The apparatus of claim 32, wherein the sum of the second Hadamard Transform of order size 2N-1 and the first Hadamard Transform of order size 2N-1 is generated during a first clock cycle and wherein the sum of the second Hadamard Transform of order size 2N-1 and the two’s complements of the first Hadamard Transform of order size 2N-1 is generated during a second clock cycle.
37. The apparatus of claim 32, wherein the sum of the second Hadamard Transform of order size 2N-1 and the first Hadamard Transform of order size 2N-1 is generated during the same clock cycle and wherein the sum of the second Hadamard Transform of order size 2N-1 and the two’s complements of the first Hadamard Transform of order size 2N-1 is generated during the same clock cycle.
38. The apparatus of claim 32, wherein the first shift register is a random access memory.
39. The apparatus of claim 32, wherein the first shift register is a FIFO register.
40. The apparatus of claim 32, wherein the first adder is shared with another channel.
41. In a signal processing device, a method for serially calculating a Fast Hadamard Transform of a sampled signal from a first channel, the method comprising:
serially storing samples of the signal;
computing a first sum of a second sample of the signal and a first sample of the signal;
storing the first sum;
computing a second sum of the second sample of the signal and a two’s complement of the first sample of the signal;
storing the second sum; and
combining the first sum and the second sum to form a sampled Hadamard Transform signal of size N of the sampled signal from the first channel,
wherein the sampled signal from the first channel is representative of a wireless communication transmitted to the signal processing device.
42. The method of claim 41, further comprising storing the first and second sums in a memory.
43. The method of claim 41, wherein the sampled signal contains 2N samples where N is an integer.
44. The method of claim 41, wherein the first sum is computed during a first clock cycle and the second sum is computed during a second clock cycle.
45. The method of claim 41, wherein the first sum is computed during the same clock cycle and the second sum is computed during the same clock cycle.