1. A security system for a computer network, the network having a plurality of devices connected thereto, at least some of the devices generating event messages when the device is under an attack, each event message having an associated event, the security system comprising:
(a) a security subsystem connected to at least the devices in the network that generate an event message when under attack, the security subsystem generating a plurality of views, each view including a subset of the event messages generated by the devices, the security subsystem including an event analyzer which analyzes the event messages across multiple views to determine if any of the associated events exceeds a predetermined threshold;
(b) a master security system which receives the associated events which exceed the predetermined threshold from the security subsystem; and
(c) a first communication medium connected between the security subsystem and the master security system, the master security system receiving the associated events through the first communication medium.
2. The system of claim 1 wherein a subset of the event messages included in one view of the plurality of views differs from a subset of the event messages included in another view of the plurality of views.
3. The system of claim 1 wherein the event analyzer comprises a plurality of view analyzers, each view analyzer analyzing the subset of the even messages included within a particular view.
4. The system of claim 1 wherein the security subsystem further includes a self-checking mechanism which performs scans of the computer network and the connected devices and generates a scan event information.
5. The system of claim 4 further comprising a system scan view, wherein the security subsystem receives the scan event information and places a certain scan event information into the system scan view if the certain scan event information matches a predetermined parameter.
6. The system of claim 1 wherein a particular subset of the event messages generated by the devices of the computer network is placed into a particular view based on a priority of the devices within the computer network.
7. The system of claim 1 wherein a particular subset of the event messages generated by the devices of the computer network is placed into a particular view based on a severity of a particular associated event.
8. The system of claim 1 wherein the master security system is located outside of the computer network.
9. The system of claim 1 wherein the security subsystem further comprises a counteraction mechanism which causes selected countering events to occur upon detection of selected events that exceed the predetermined threshold.
10. The system of claim 5 wherein the countering events include restricting or disabling access to the network or a device in the network.
11. The system of claim 1 wherein the master security system is hierarchically independent from the security subsystem.
12. The system of claim 1 wherein the security subsystem is hierarchically subordinate to the master security system.
13. The system of claim 1 wherein the first communication medium is a secure link defined by a virtual private network (VPN) tunnel.
14. The system of claim 1 wherein the master system further comprises a pseudo-attack generator which generates attacks on the network, the security subsystem detecting such attacks and sending expected replies to the master system when its integrity is intact, the master system detecting whether the expected replies are received in response to a pseudo-attack to determine whether the integrity of the subsystem has been compromised.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
That which is claimed is:
1. Circuit (CC1;CC2;CC1) to control the impedance of an output driving stage OB of an integrated circuit comprising a plurality of driving transistors (p1-p3,n1-n3) including at least one enablingdisabling transistor (p1;n1), said control circuit comprising:
variable impedance means (p1;n1;P0) whose impedance varies with the temperature in correlation with the impedance of said output driving stage,
control means (9;19,50) connected to said variable impedance means to generate a first enablingdisabling signal of said at least one transistor based on a control signal correlated to the impedance of the variable impedance means; characterized in that it further comprises:
means (8;18) to generate a current so as to inject into said variable impedance means a current which remains substantially stable as the temperature varies.
2. Control circuit (CC1;CC2,CC1) according to claim 1 wherein said control signal is correlated to the voltage drop in said variable impedance (p1;n1;P0) determined by said current.
3. Control circuit CC1;CC2,CC1) according to claim 1 wherein said current generation means (8;18) comprise a current source (60) to generate a reference current which remains substantially stable as the temperature varies and as the supply voltage varies.
4. Control circuit (CC1;CC2,CC1) according to claim 3 wherein said source (60) includes a reference voltage generator of the bandgap type.
5. Control circuit (CC1;CC2,CC1) according to claim 3 wherein said current generation means (8;18) comprise a multiplication circuit connected to said current source (60) and including at least one current mirror (CM1,CM2) to multiply the reference current by a multiplication factor and obtain said current which remains substantially stable as the temperature varies.
6. Control circuit (CC1;CC2,CC1) according to claim 5 wherein, between said current source (60) and said multiplication circuit (CM1,CM2), a current mirror (CM) is interposed to supply the multiplication circuit with a current proportional to the reference current.
7. Control circuit (CC1;CC2,CC1) according to claim 5 wherein said multiplication circuit comprises a first current mirror (CM1) having a first current multiplying factor and a second current mirror (CM2) connected to said first mirror to multiply by a second multiplication factor a current coming from the first mirror and provide said current which remains substantially stable as the temperature varies.
8. Control circuit (CC1;CC2,CC1) according to claim 1 wherein said control means comprises a comparator (9;19;51) provided with a first input for said control signal, a second input for a reference signal, said comparator supplying a difference signal depending on the difference between said control and reference signals, bases on which it is possible to obtain said first enablingdisabling signal.
9. Control circuit (CC1) according to claim 8, further comprising a counting device (52) for the bi-directional counting of timing pulses, provided with an input terminal connected to the comparator output (51) to receive a counting direction control signal, and with at least one counting output connected to said variable impedance means to supply counting signals such as to vary their impedance.
10. Control circuit (CC1) according to claim 9, further comprising:
a register (54) for storing said counting signals, it being possible to activate said register by means of an activation signal to supply said first output enablingdisabling signal;
a sequence identifier (53) connected to said comparator (51) and to said register (54) to identify a sequence of said counting signals and feed the activation signal to the register.
11. Control circuit (CC1;CC2,CC1) according to claim 1 wherein said variable impedance means (p1;n1;P0) comprise at least one control transistor.
12. Control circuit (CC1;CC2;CC1) according to claim 1 wherein the control circuit and output driving stage (OB) can be fed by a supply voltage, the variable impedance means (p1;n1;P0) having an impedance which varies with the supply voltage according to the impedance of said output driving stage (OB) and a current which remains substantially stable as the temperature varies, being variable in correlation to said supply voltage.
13. Control circuit (CC1;CC2;CC1) according to claim 12 wherein said current varies proportionally to said supply voltage.
14. Control circuit (CC1;CC2;CC1) according to claims 5 and 13 wherein said at least one current mirror (CM2) comprises a plurality of multiplication branches which can be enabled selectively to modify said current proportionally to said supply voltage.
15. Control circuit (CC1;CC2;CC1) according to claim 14 wherein each branch of said plurality is connected to an enabling circuit (30) such as to generate a plurality of enablingdisabling signals of each branch according to the supply voltage and a reference voltage which remains substantially stable as the temperature varies and as the supply voltage varies.
16. Control circuit (CC1;CC2;CC1) according to claim 15 wherein said reference voltage can be generated by a voltage generator of the bandgap type.
17. Control circuit (CC1;CC2;CC1) according to claim 15 wherein said enabling circuit (30) comprises: a resistive divider (31) to which said supply voltage is applied and including a group of resistors (R1-R4), a group of comparators (C3-C5) each having a first input connected to a resistor of said group and a second input connected to the reference voltage and an output connected to a branch of said plurality of multiplication branches to supply a signal of said plurality of enablingdisabling signals.
18. Control circuit (CC1;CC2;CC1) according to claim 14 wherein each multiplication branch of said plurality comprises a multiplication transistor (Qn3) serially connected to a branch enabling transistor (Qa3).
19. Ouput driving circuit (1) for an integrated circuit comprising:
a plurality of driving transistors (p1-p3,n1-n3) to supply an output signal on an output terminal (2), said plurality of transistors including at least one enablingdisabling transistor (p1;n1);
an impedance control circuit connected to said at least one transistor to supply a first enablingdisabling signal of said at least one transistor;
characterized in that said control circuit (CC1;CC2) is provided according to at least one of the claims from 1 to 18.
20. Output driving circuit (1) according to claim 19 wherein said output terminal (2) can be connected to a data line (3) having a characteristic impedance for carrying said output signal.
21. Output driving circuit (1) according to claim 20 wherein, when operating, the driving circuit has an overall resistance substantially equal to the impedance characteristic of said data line (3).
22. Output driving circuit (1) according to claim 19 wherein said plurality of driving transistors comprises a first plurality of pull-up transistors (PU) connected in parallel and a second plurality of pull-down transistors (PD) connected in parallel, each of said pull-up transistors being connected respectively in series to each of said pull-down transistors.
23. Output driving circuit (1) according to claim 12 wherein said plurality of driving transistors is supplied with said supply voltage.
24. Output driving circuit (1) according to claim 23 wherein said output terminal (2), when switching from one logic level to the opposite logic level and when it is connected to a respective signal data line, has a voltage referred to the ground substantially equal to half of said supply voltage.
25. Output driving circuit (1) according to claim 19 wherein said control transistor (p1,n1) and said at least one transistor (p1,n1) are of the MOSFET type and the aspect ratio of the control transistor is proportional according to a factor to the aspect ratio of said at least one transistor.
26. Output driving circuit (1) according to claim 22 wherein said factor is less than 1.
27. Integrated circuit (40) comprising:
a nonvolatile memory array (41) comprising cells for storing data arranged in rows and columns;
a row (42) and column (43) decoder operationally associated to said memory array to select at least one memory cell of said array according to an address signal (ADD);
at least one sense amplifier (45) to detect said at least one stored data in said at least one memory cell;
at least one output driving circuit (ODC1) provided with an input connected to the output of said at least one sense amplifier to receive said at least one data and an output terminal for said at least one data which can be connected to a data line (TL1) external to the integrated circuit,
characterized in that said at least one driving circuit (ODC1) is provided according to at least one of the claims from 19 to 26.