1. A method for phase-timing compensation for a design, comprising:
identifying a clock source for a path;
identifying a clock sink for the path;
obtaining an absolute path slack for the path;
determining phase offset of the clock source relative to the clock sink;
generating a normalizing factor responsive to the phase offset; and
computing a normalized slack using the absolute path slack and the normalizing factor.
2. A method for phase-timing compensation for a design, comprising:
identifying a path of the design;
identifying an interconnect resource of the path;
obtaining a delay specification for the path;
obtaining a propagation delay of the interconnect resource;
obtaining an arrival time for a path source of the path to the interconnect resource;
obtaining a destination time from the interconnect resource to a path sink;
determining absolute path slack of the interconnect resource responsive to the arrival time, the destination time and the propagation delay; and
normalizing the absolute path slack;
the normalizing of the absolute slack including:
determining a phase offset of a clock source of the path relative to the clock sink of the path;
generating a normalizing factor responsive to the phase offset; and
multiplying the absolute slack by the normalizing factor.
3. The method, according to claim 2, wherein the propagation delay of the interconnect resource is a maximum propagation delay.
4. The method, according to claim 2, wherein the arrival time comprises a maximum delay of all path sources to the interconnect resource.
5. The method, according to claim 4, wherein the maximum delay is determined taking into account each predecessor resource between the path source and the interconnect resource.
6. The method, according to claim 2, wherein the destination time comprises a minimum of maximum delays from the interconnect resource to all path sinks.
7. The method, according to claim 6, wherein the minimum of maximum delays is determined taking into account each successor resource between the interconnect resource and the path sink.
8. A method for phase-timing compensation for a design, comprising:
obtaining a path of said design;
identifying an interconnect resource of said path;
obtaining a propagation delay of said interconnect resource;
identifying each clock source and each clock sink of said path;
determining a destination time from said interconnect resource to each said clock sink;
determining a phase-shift offset of each said clock source relative to said clock sink;
determining a normalized arrival time of each said clock source to said interconnect resource;
determining a phase-shift factor for each said clock source to said interconnect resource respectively responsive to each said phase-shift offset; and
determining a normalized slack for said interconnect resource responsive to said phase-shift factor, said normalized arrival time, said propagation delay, and said destination time.
9. The method, according to claim 8, wherein each said clock source is a digital clock module configured to provide a plurality of clock signals.
10. The method, according to claim 9, wherein said digital clock module is part of a programmable logic device.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A switching power supply controller comprising:
a first comparator to compare a feedback signal to a first limit to set a flip-flop to a first operating state of the power supply controller and a second comparator to compare the feedback signal to a second limit to set the flip-flop to a second operating state of the power supply controller, wherein the first limit comprises a ramp.
2. The controller of claim 1 where the second limit comprises a ramp.
3. The controller of claim 1 where the second limit comprises a bias signal.
4. The controller of claim 1 where the feedback signal comprises an error signal.
5. The controller of claim 1 further comprising a feedback network coupled to the comparator to generate the feedback signal responsive to an output signal.
6. The controller of claim 5 where the feedback network comprises an error amplifier to generate the feedback signal responsive to an input control signal and an output signal.
7. The controller of claim 6 where the output signal represents a voltage.
8. The controller of claim 6 where the output signal represents a current.
9. The controller of claim 1 further comprising a limit generator coupled to the comparator to generate the first limit.
10. The controller of claim 9 where the limit generator is to generate the first limit in response to a power supply signal.
11. The controller of claim 9 where the limit generator is to generate the first limit in response to an input control signal.
12. The controller of claim 9 where the limit generator is to generate the first limit in response to an output signal.
13. The controller of claim 9 further comprising a second limit generator coupled to the comparator to generate the second limit.
14. The controller of claim 13 where the second limit generator is to generate the second limit in response to a power supply signal.
15. The controller of claim 13 where the second limit generator is to generate the second limit in response to an input control signal.
16. A switching power supply controller comprising:
a comparator to compare a feedback signal to a first limit to set a first operating state of the power supply controller and to a second limit to set a second operating state of the power supply controller, wherein the first limit comprises a ramp;
a first limit generator coupled to the comparator to generate the first limit in response to a power supply signal, an input control signal, andor an output signal;
a second limit generator coupled to the comparator to generate the second limit in response to a power supply signal andor an input control signal; and
an error amplifier coupled to the comparator to generate the feedback signal in response to an output signal and an input control signal.
17. A method comprising:
operating a switching power supply between first and second states in order to regulate an output voltage by comparing a feedback signal to a first limit to set a modulation signal used to regulate the output voltage and comparing the feedback signal to a second limit to reset the modulation signal, wherein the second limit is a ramp.
18. The method of claim 17 where the second limit is a ramp.
19. The method of claim 17 where the second limit is a bias signal.
20. The method of claim 17 further comprising generating the feedback signal in response to an output signal and an input control signal.
21. The method of claim 17 further comprising generating the first limit in response to an output signal.
22. A switching power supply controller comprising:
a means for comparing an error signal to a bias signal and responsively setting a modulation signal used to regulate an output voltage; and
a separate means for comparing the error signal to a ramp signal and responsively resetting the modulation signal.
23. The controller of claim 22 further comprising means for generating the error signal in response to an output signal and an input control signal.
24. The controller of claim 22 further comprising means for generating the ramp signal.
25. The controller of claim 22 further comprising means for generating the bias signal.