1. A folding top for a vehicle having at least one roof part that can be displaced between a closed position and a stowed position that is within the vehicle, and can be brought out of the stowed position into a loading position which is raised with respect to the stowed position, the folding top having a folding-top kinematic mechanism which has, on each side of the at least one roof part, a main bearing element and an intermediate bearing element mounted rotatably on the main bearing element at a first pivot point, and the at least one roof part being coupled both to the main bearing element and to the intermediate bearing element via links on both sides of the folding-top kinematic mechanism, and being displaceable by means of at least one driving device, wherein:
the driving device has at least one linear driving element which acts at least indirectly on the intermediate bearing element at a second pivot point which is remote from the first pivot point;
a first device is provided for limiting rotational movement of the intermediate bearing element during movement of the at least one roof part from the stowed position into the closed position;
the roof part has mass which acts on the second pivot point via the links, such that during the movement of the roof part from the stowed position into the closed position, a movement of the links is possible only after the rotational movement of the intermediate bearing element has ended; and
a second device is provided for preventing movement of the intermediate bearing element during the movement of the roof part from the closed position into the loading position.
2. The folding top according to claim 1, wherein the link is guided by means of a guide device at least during the movement of the roof part from the closed position into the loading position.
3. A folding top for a vehicle having at least one roof part that can be displaced between a closed position and a stowed position that is within the vehicle, and can be brought out of the stowed position into a loading position which is raised with respect to the stowed position, the folding top having a folding-top kinematic mechanism which has, on each side of the at least one roof part, a main bearing element and an intermediate bearing element mounted rotatably on the main bearing element at a first pivot point, and the at least one roof part being coupled both to the main bearing element and to the intermediate bearing element via links on both sides of the folding-top kinematic mechanism, and being displaceable by means of at least one driving device, wherein:
the driving device has at least one linear driving element which acts at least indirectly on the intermediate bearing element at a second pivot point which is remote from the first pivot point;
a first device is provided for limiting rotational movement of the intermediate bearing element during movement of the at least one roof part from the stowed position into the closed position;
the link is guided by a guide device at least during the movement of the roof part from the closed position into the loading position; and
a second device is provided for preventing movement of the intermediate bearing element during the movement of the roof part from the closed position into the stowed position.
4. The folding top according to claim 3, wherein, during their movement between the loading position and the stowed position, the links of the folding-top kinematic mechanism are guided by the guide device.
5. The folding top according to claim 4, wherein the links of the folding-top kinematic mechanism are attached rotatably to the intermediate bearing elements at the point at which the linear driving elements act on the intermediate bearing elements.
6. The folding top according to claim 5, wherein each of the guide devices has a guide track formed in the main bearing element and a bolt which engages in the guide track and is attached to the link of the folding-top kinematic mechanism.
7. The folding top according to claim 6, wherein the guide tracks each have a track section assigned to movement of the links between the closed position and the loading position, and a track section assigned to the movement of the links between the loading position and the stowed position.
8. The folding top according to claim 7, wherein:
the track section which is assigned to the movement of the links between the closed position and the loading position is circular, and has a center point that corresponds to the second pivot point; and
the track section which is assigned to movement of the links between the loading position and the stowed position is circular, and has a center point.
9. The folding top according to claim 5, wherein each of the guide devices has a blocking element attached moveably to the intermediate bearing element and a bolt which is in engagement with the blocking element during the movement of the roof parts between the loading position and the stowed position and is attached to the link of the folding-top kinematic mechanism.
10. The folding top according to claim 9, wherein a fixed stop element is provided for the blocking element, against which the latter strikes on reaching the loading position and releases the bolt.
11. The folding top according to claim 10, wherein after the loading position is reached the bolt is guided in a track section assigned to movement of the links between the loading position and the stowed position.
12. The folding top according to claim 11, wherein the blocking element is pressed into position engaging around the bolt by means of a spring element.
13. The folding top according to claim 5, wherein the guide device has a blocking element that is engaged with a rigid element during movement of the roof parts between the closed position and the loading position.
14. The folding top according to claim 13, wherein the blocking element is operable by a connecting lever connecting the intermediate bearing element to the linear driving element, to bring the blocking element into a position releasing the intermediate bearing element.
15. The folding top according to claim 14, wherein a lever arrangement with at least two levers is provided between the linear driving element and the intermediate bearing element, one of the levers being connected on the one hand to the linear driving element and on the other hand to the intermediate bearing element and the other lever being connected on the one hand to the linear driving element and on the other hand to the link.
16. The folding top according to claim 15, wherein the guide device has a recess in the main bearing element, in which a projection that is attached to the lever connected to the intermediate bearing element engages during the movement of the roof parts between the closed position and the loading position, for locking the intermediate bearing element in relation to the main bearing element.
17. A convertible vehicle comprising a folding top having at least one roof part that can be displaced between a closed position and a stowed position that is within the vehicle, and can be brought out of the stowed position into a loading position which is raised with respect to the stowed position, the folding top having a folding-top kinematic mechanism which has, on each side of the at least one roof part, a main bearing element and an intermediate bearing element mounted rotatably on the main bearing element at a first pivot point, and the at least one roof part being coupled both to the main bearing element and to the intermediate bearing element via links on both sides of the folding-top kinematic mechanism, and being displaceable by means of at least one driving device, wherein:
the driving device has at least one linear driving element which acts at least indirectly on the intermediate bearing element at a second pivot point which is remote from the first pivot point;
a first device is provided for limiting rotational movement of the intermediate bearing element during movement of the at least one roof part from the stowed position into the closed position;
the roof part has mass which acts on the second pivot point via the links, such that during the movement of the roof part from the put-away position into the closed position, a movement of the links is possible only after the rotational movement of the intermediate bearing element has ended; and
a second device is provided for preventing movement of the intermediate bearing element during the movement of the roof part from the closed position into the loading position.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A memory component with built-in self test, comprising:
an inputoutput interface having a loopback;
a controller to transmit inputoutput test data to the inputoutput interface, and to receive the inputoutput test data from the loopback of the inputoutput interface; and
a compare register to store and compare the inputoutput test data transmitted to the inputoutput interface with the inputoutput test data received from the inputoutput interface, wherein the memory component resides within a memory module having a plurality of memory devices and at least one buffer.
2. The memory component according to claim 1, wherein the memory component is a dynamic random access memory (DRAM).
3. The memory component according to claim 1, wherein the memory component is a buffer.
4. The memory component according to claim 3, wherein the buffer is an address and command buffer.
5. The memory component according to claim 3, wherein the buffer is a data buffer.
6. The memory component according to claim 3, wherein the buffer is an address and command and data buffer.
7. The memory component according to claim 1, wherein the compare register generates a test result based on the inputoutput test data transmitted to the inputoutput interface compared with the inputoutput test data received from the inputoutput interface.
8. The memory component according to claim 1, wherein the controller is adapted to transmit memory array test data to a memory array to store the test data therein, and to read the memory array test data from the memory array, and the compare register is adapted to compare the memory array test data transmitted to the memory array with the memory array test data read from the memory array.
9. A memory component with built-in self test, comprising:
a memory array;
an inputoutput interface coupled to the memory array and having a loopback;
a controller to transmit memory array test data to the memory array to store the memory array test data, and to read the memory array test data from the memory array; and
a compare register to store and compare the memory array test data transmitted to the memory array with the memory array test data read from the memory array, wherein the memory component resides within a memory module having a plurality of memory devices and at least one buffer.
10. The memory component according to claim 9, wherein the memory component is a dynamic random access memory (DRAM).
11. The memory component according to claim 9, wherein the memory component is a buffer.
12. The memory component according to claim 11, wherein the buffer is an address and command buffer.
13. The memory component according to claim 11, wherein the buffer is a data buffer.
14. The memory component according to claim 11, wherein the buffer is an address and command and data buffer.
15. The memory component according to claim 9, wherein the compare register generates a test result based on the memory array test data transmitted to the memory array compared with the memory array test data read from the memory array.
16. A method of testing a memory component with built-in self test, comprising:
transmitting inputoutput test data to an inputoutput interface having a loopback;
receiving the inputoutput test data from the loopback of the inputoutput interface;
storing the inputoutput test data transmitted to the inputoutput interface and the inputoutput test data received from the inputoutput interface in a register; and
comparing the inputoutput test data transmitted to the inputoutput interface with the inputoutput test data received from the inputoutput interface, wherein the memory component resides within a memory module having a plurality of memory devices and at least one buffer.
17. The method according to claim 16, wherein the memory component is a dynamic random access memory (DRAM).
18. The method according to claim 16, wherein the memory component is a buffer.
19. The method according to claim 18, wherein the buffer is an address and command buffer.
20. The method according to claim 18, wherein the buffer is a data buffer.
21. The method according to claim 18, wherein the buffer is an address and command and data buffer.
22. The method according to claim 18, wherein the buffer is an address and command buffer.
23. The method according to claim 18, wherein the buffer is a data buffer.
24. The method according to claim 18, wherein the buffer is an address and command and data buffer.
25. The method according to claim 16, wherein the compare register generates a test result based on the inputoutput test data transmitted to the inputoutput interface compared with the inputoutput test data received from the inputoutput interface.
26. The method according to claim 16, further including:
transmitting memory array test data to a memory array;
storing the memory array test data in the memory array;
reading the memory array test data from the memory array; and
comparing the memory array test data transmitted to the memory array with the memory array test data read from the memory array.
27. The method according to claim 24, wherein the memory component is a dynamic random access memory (DRAM).
28. The method according to claim 24, wherein the memory component is a buffer.
29. A method of testing a memory component with built-in self test, comprising:
transmitting memory array test data to a memory array;
storing the memory array test data in the memory array;
reading the memory array test data from the memory array;
storing the memory array test data transmitted to the memory array and the memory array test data read from the memory array in a register; and
comparing the memory array test data transmitted to the memory array with the memory array test data read from the memory array, wherein the memory component resides within a memory module having a plurality of memory devices and at least one buffer.
30. The method according to claim 29, wherein the memory component is a dynamic random access memory (DRAM).
31. The method according to claim 29, wherein the memory component is a buffer.
32. The method according to claim 31, wherein the buffer is an address and command buffer.
33. The method according to claim 31, wherein the buffer is a data buffer.
34. The method according to claim 31, wherein the buffer is an address and command and data buffer.
35. The method according to claim 29, wherein the compare register generates a test result based on the memory array test data transmitted to the memory array compared with the memory array test data read from the memory array.
36. A memory module with built-in self test, comprising:
a plurality of memory components;
an address and command buffer adapted to transmit address and command data and test data to one of the plurality of memory components, wherein the address and command buffer includes a register to receive a test result; and
at least one data buffer to receive the test data from the address and command buffer, to receive the test data from the one of the plurality of memory components, and to compare the test data received from the address and command buffer with the test data received from the one of the plurality of memory components to generate the test result, wherein the plurality of memory components, the address and command buffer, and the at least one data buffer all reside within the memory module.
37. The memory module according to claim 36, wherein the address and command buffer and the data buffer are within a single buffer chip.
38. The memory module according to claim 36, wherein the at least one memory component is a dynamic random access memory (DRAM).
39. The memory module according to claim 36, wherein the address and command buffer includes a clock multiplier to receive a clock signal and to multiply the clock signal for transmission to the at least one memory component and the at least one data buffer.
40. The memory module according to claim 36, wherein the address and command buffer includes an address and command generator to generate the address and command data.
41. The memory module according to claim 36, wherein the test data is obtained from a data bus through a memory controller.
42. The memory module according to claim 36, wherein the register receives the test result from the at least one data buffer and reports the test result as one of the following conditions: built-in self test not enabled, built-in self test enabled, built-in self test failed, and built-in self test passed.
43. The memory module according to claim 36, wherein the at least one data buffer utilizes an exclusive-OR (XOR) comparator to compare the test data received from the address and command buffer with the test data received from the at least one memory component.
44. A method of testing a memory module with built-in self test, the method comprising:
transmitting address and command data and test data to a memory component among a plurality of memory components from an address and command buffer, wherein the plurality of memory components and the address and command buffer all reside within the memory module;
receiving the test data from the address and command buffer;
receiving the test data from the memory component; and
comparing the test data received from the address and command buffer with the test data received from the memory component to generate a test result.
45. The method according to claim 44, wherein receiving the test data from the address and command buffer, receiving the test data from the memory component, and comparing the test data are performed in a data buffer.
46. The method according to claim 45, wherein the data buffer and the address and command buffer are within a single buffer chip.
47. The method according to claim 44, wherein the memory component is a dynamic random access memory (DRAM).
48. The method according to claim 44, further including:
receiving a clock signal by a clock multiplier of the address and command buffer;
multiplying the clock signal; and
transmitting the clock signal to the memory component and a data buffer.
49. The method according to claim 44, further including:
generating the address and command data from an address and command data generator of the address and command buffer.
50. The method according to claim 44, further including:
obtaining the test data from a data bus through a memory controller.
51. The method according to claim 44, further including:
receiving the test result in a register of the address and command buffer; and
reporting the test result from the register as one of the following conditions: built-in self test not enabled, built-in self test enabled, built-in self test failed, and built-in self test passed.
52. The method according to claim 44, wherein comparing the test data received from the address and command buffer with the test data received from the memory component is performed by a data buffer utilizing an exclusive-OR (XOR) comparator.
53. A memory module with built-in self test, comprising:
a plurality of memory components;
an address and command buffer adapted to transmit address and command data and test data to one of the plurality of memory components, wherein the address and command buffer includes,
a register to receive a test result,
a clock multiplier to receive a clock signal and to multiply the clock signal for transmission, and
an address and command generator to generate the address and command data; and
at least one data buffer to receive the test data from the address and command buffer, to receive the test data from the one of the plurality of memory components, and to compare the test data received from the address and command buffer with the test data received from the one of the plurality of memory components to generate the test result, wherein the plurality of memory components, the address and command buffer, and the at least one data buffer all reside within the memory module.
54. The memory module according to claim 53, wherein the address and command buffer and the data buffer are within a single buffer chip.
55. The memory module according to claim 53, wherein the at least one memory component is a dynamic random access memory (DRAM).
56. The memory module according to claim 53, wherein the test data is obtained from a data bus through a memory controller.
57. The memory module according to claim 53, wherein the register receives the test result from the at least one data buffer and reports the test result as one of the following conditions: built-in self test not enabled, built-in self test enabled, built-in self test failed, and built-in self test passed.
58. The memory module according to claim 53, wherein the at least one data buffer utilizes an exclusive-OR (XOR) comparator to compare the test data received from the address and command buffer with the test data received from the at least one memory component.
59. A memory component with built-in self test, comprising:
a memory array;
an inputoutput interface coupled to the memory array and having a loopback;
a controller to transmit memory array and test data to the memory array to store the memory array test data, to read the memory array test data from the memory array, to receive the memory array test data from the loopback of the inputoutput interface that was transmitted by the memory array to the inputoutput interface, to transmit inputoutput test data to the inputoutput interface, and to receive the inputoutput test data from the loopback of the inputoutput interface; and
a compare register to store and compare the memory array test data transmitted to the memory array with the memory array test data read from the memory array, to store and compare the memory array test data transmitted to the memory array with the memory array test data received from the loopback of the inputoutput interface that was transmitted from the memory array, and to store and compare the inputoutput test data transmitted to the inputoutput interface with the inputoutput test data received from the loopback of the inputoutput interface, wherein the compare register generates a test result based on the memory array test data transmitted to the memory array compared with the memory array test data read from the memory array, generates a test result based on the memory array test data transmitted to the memory array compared with the memory array test data received from the loopback of the inputoutput interface that was transmitted by the memory array to the inputoutput interface, and generates a test result based on the inputoutput test data transmitted to the inputoutput interface compared with the inputoutput test data received from the loopback of the inputoutput interface.
60. The memory component according to claim 59, wherein the memory component is a dynamic random access memory (DRAM).
61. The memory component according to claim 59, wherein the memory component is a buffer.
62. The memory component according to claim 61, wherein the buffer is an address and command buffer.
63. The memory component according to claim 61, wherein the buffer is a data buffer.
64. A method of testing a memory component with built-in self test, comprising:
transmitting memory array test data to a memory array to store the memory array test data;
reading the memory array test data from the memory array;
receiving the memory array test data from a loopback of an inputoutput interface that was transmitted by the memory array to the inputoutput interface;
transmitting inputoutput test data to the inputoutput interface;
receiving the inputoutput test data from the loopback of the inputoutput interface;
storing and comparing the memory array test data transmitted to the memory array with the memory array test data read from the memory array;
storing and comparing the memory array test data transmitted to the memory array with the memory array test data received from the loopback of the inputoutput interface that was transmitted from the memory array;
storing and comparing the inputoutput test data transmitted to the inputoutput interface with the inputoutput test data received from the loopback of the inputoutput interface;
generating a test result based on the memory array test data transmitted to the memory array compared with the memory array test data read from the memory array;
generating a test result based on the memory array test data transmitted to the memory array compared with the memory array test data received from the loopback of the inputoutput interface that was transmitted by the memory array to the inputoutput interface; and
generating a test result based on the inputoutput test data transmitted to the inputoutput interface compared with the inputoutput test data received from the loopback of the inputoutput interface.