1. A method of manufacturing a flash memory device, the method comprising:
forming a storage node layer on a semiconductor substrate;
after forming the storage node layer, forming a dummy layer within the storage node layer to separate the storage node layer into at least two storage nodes; and
forming spacer-shaped control gates on both sidewalls of the dummy layer so that each control gate covers a sidewall and a top surface of a corresponding storage node.
2. The method of claim 1, further comprising, before and after the forming of the storage node, forming an insulating layer.
3. The method of claim 1, wherein the forming of the storage node layer and the forming of the dummy layer comprise:
sequentially stacking a semiconductor tunnel oxide layer, a storage node layer, and a gate insulating layer;
forming a damascene molding layer on the gate insulating layer;
forming a patterned dummy layer using a damascene method so that the dummy layer partially passes through the damascene molding layer, the gate insulating layer, the storage node layer, and the tunnel oxide layer;
removing the damascene molding layer;
forming dummy spacers on both sidewalls of the dummy layer; and
patterning the gate insulating layer, the storage node layer, and the tunnel oxide layer using the dummy spacers as masks; and
removing the dummy spacers.
4. The method of claim 3, wherein the forming of the control gates comprises:
forming a gate insulating layer on sidewalls of the dummy layer and a surface of the semiconductor substrate;
forming conductive spacers on the sidewalls of the dummy layer coated with the gate insulating layer; and
removing the dummy layer.
5. The method of claim 1, wherein the forming of the storage node layer and the forming of the dummy layer comprise:
sequentially stacking a semiconductor tunnel oxide layer, a storage node layer, and a gate insulating layer;
forming a damascene molding layer on the gate insulating layer;
forming a patterned dummy layer using a damascene method so that the dummy layer partially passes through the damascene molding layer, the gate insulating layer, the storage node layer, and the tunnel oxide layer;
removing the damascene molding layer;
forming first conductive spacers on both sidewalls of the dummy layer; and
patterning the gate insulating layer, the storage node layer, and the tunnel oxide layer using the first conductive spacers as masks.
6. The method of claim 5, wherein the forming of the control gates comprises:
forming a gate insulating layer on sidewalls of the first conductive spacers, a sidewall of each storage node, and a surface of the semiconductor substrate;
forming a second conductive spacer on a sidewall of each of the first conductive spacers coated with the gate insulating layer; and removing the dummy layer.
7. The method of claim 6, further comprising, after the forming of the control gates, forming a silicide layer that electrically connects the first conductive spacer and the second conductive spacer.
8. The method of claim 1, wherein the forming of the storage node layer and the forming of the dummy layer comprise:
sequentially stacking a semiconductor tunnel oxide layer, a storage node layer, and a gate insulating layer;
forming a damascene molding layer on the gate insulating layer;
forming a patterned dummy layer using a damascene method so that the dummy layer partially passes through the damascene molding layer, the gate insulating layer, the storage node layer, and the tunnel oxide layer;
removing the damascene molding layer;
forming first conductive spacers on both sidewalls of the dummy layer;
patterning the gate insulating layer, the storage node layer, and the tunnel oxide layer using the first conductive layers as masks; and removing the dummy layer.
9. The method of claim 8, wherein the forming of the control gates comprises:
forming a gate insulating layer on the resultant semiconductor substrate; and
forming second conductive spacers on both sidewalls of each of the first conductive spacers coated with the gate insulating layer.
10. The method of claim 8, further comprising, after the forming of the control gates, forming a silicide layer that electrically connects the first conductive spacers and the second conductive spacers.
11. A method of manufacturing a flash memory device, the method comprising:
forming a storage node layer on a semiconductor substrate;
forming a dummy layer within the storage node layer to separate the storage node layer into at least two storage nodes, wherein the forming of the storage node layer and the forming of the dummy layer comprise:
sequentially stacking a semiconductor tunnel oxide layer, a storage node layer, and a gate insulating layer;
forming a damascene molding layer on the gate insulating layer;
forming a patterned dummy layer using a damascene method so that the dummy layer partially passes through the damascene molding layer, the gate insulating layer, the storage node layer, and the tunnel oxide layer;
removing the damascene molding layer;
forming dummy spacers on both sidewalls of the dummy layer;
patterning the gate insulating layer, the storage node layer, and the tunnel oxide layer using the dummy spacers as masks; and
removing the dummy spacers; and
forming spacer-shaped control gates on both sidewalls of the dummy layer so that each control gate covers a sidewall and a top surface of a corresponding storage node.
12. The method of claim 11, wherein the forming of the control gates comprises:
forming a gate insulating layer on sidewalls of the dummy layer and a surface of the semiconductor substrate;
forming conductive spacers on the sidewalls of the dummy layer coated with the gate insulating layer; and
removing the dummy layer.
13. A method of manufacturing a flash memory device, the method comprising:
forming a storage node layer on a semiconductor substrate;
forming a dummy layer within the storage node layer to separate the storage node layer into at least two storage nodes, wherein forming the storage node layer and forming the dummy layer comprise:
sequentially stacking a semiconductor tunnel oxide layer, a storage node layer, and a gate insulating layer;
forming a damascene molding layer on the gate insulating layer;
forming a patterned dummy layer using a damascene method so that the dummy layer partially passes through the damascene molding layer, the gate insulating layer, the storage node layer, and the tunnel oxide layer;
removing the damascene molding layer;
forming first conductive spacers on both sidewalls of the dummy layer; and
patterning the gate insulating layer, the storage node layer, and the tunnel oxide layer using the first conductive spacers as masks; and
forming spacer-shaped control gates on both sidewalls of the dummy layer so that each control gate covers a sidewall and a top surface of a corresponding storage node.
14. The method of claim 13, wherein the forming of the control gates comprises:
forming a gate insulating layer on sidewalls of the first conductive spacers, a sidewall of each storage node, and a surface of the semiconductor substrate;
forming a second conductive spacer on a sidewall of each of the first conductive spacers coated with the gate insulating layer; and
removing the dummy layer.
15. The method of claim 14, further comprising, after the forming of the control gates, forming a silicide layer that electrically connects the first conductive spacer and the second conductive spacer.
16. A method of manufacturing a flash memory device, the method comprising:
forming a storage node layer on a semiconductor substrate;
forming a dummy layer within the storage node layer to separate the storage node layer into at least two storage nodes, wherein forming the storage node layer and forming the dummy layer comprise:
sequentially stacking a semiconductor tunnel oxide layer, a storage node layer, and a gate insulating layer;
forming a damascene molding layer on the gate insulating layer;
forming a patterned dummy layer using a damascene method so that the dummy layer partially passes through the damascene molding layer, the gate insulating layer, the storage node layer, and the tunnel oxide layer;
removing the damascene molding layer;
forming first conductive spacers on both sidewalls of the dummy layer;
patterning the gate insulating layer, the storage node layer, and the tunnel oxide layer using the first conductive layers as masks; and
removing the dummy layer; and
forming spacer-shaped control gates on both sidewalls of the dummy layer so that each control gate covers a sidewall and a top surface of a corresponding storage node.
17. The method of claim 16, wherein the forming of the control gates comprises:
forming a gate insulating layer on the resultant semiconductor substrate; and
forming second conductive spacers on both sidewalls of each of the first conductive spacers coated with the gate insulating layer.
18. The method of claim 16, further comprising, after the forming of the control gates, forming a silicide layer that electrically connects the first conductive spacers and the second conductive spacers.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A wavelength selective device comprising:
an input port for inputting an optical beam;
a tiltable MEMS mirror optically coupled to the input port, for reflecting the optical beam;
a focusing element optically coupled to the MEMS mirror, for focusing the reflected optical beam into a focal spot displaceable by varying an angle of tilt of the MEMS mirror;
an arrayed waveguide grating comprising an input slab having an elongate aperture for receiving the focal spot, and a plurality of output waveguides for outputting wavelength sub-beams of the optical beam, wherein the input slab is disposed so that when the angle of tilt of the MEMS mirror is varied, the focal spot is displaced along the elongate aperture;
a temperature sensor thermally coupled to the arrayed waveguide grating, for sensing a change of temperature thereof; and
a controller electrically coupled to the temperature sensor and the tiltable MEMS mirror, and configured for varying the angle of tilt upon sensing the arrayed waveguide temperature change by the temperature sensor, so as to lessen a wavelength drift of the wavelength sub-beams induced by the temperature change.
2. The wavelength selective device of claim 1, wherein the controller has a power rating of 10 mW or less.
3. The wavelength selective device of claim 2, wherein the controller has a power rating of 1 mW or less.
4. The wavelength selective device of claim 1, further comprising an input waveguide having an input end optically coupled to the input port, and an output end optically coupled to the tiltable MEMS mirror.
5. The wavelength selective device of claim 4, wherein the output end is coupled to the tiltable MEMS mirror via the focusing element.
6. The wavelength selective device of claim 4, further comprising a splitter optically coupled to the input waveguide, for splitting a portion of the optical beam, wherein the wavelength selective device includes a photoelectric generator optically coupled to the splitter, for receiving the split portion of the optical beam, and converting the received portion into electrical power for powering the controller.
7. The wavelength selective device of claim 6, wherein the photoelectric generator has a maximum power rating of 10 mW or less.
8. The wavelength selective device of claim 7, wherein the photoelectric generator has a maximum power rating of 1 mW or less.
9. The wavelength selective device of claim 6, wherein the splitter is wavelength-selective, so that the split portion has a different wavelength than the wavelength sub-beams.
10. The wavelength selective device of claim 6, wherein the photoelectric generator comprises a photovoltaic cell.
11. The wavelength selective device of claim 1, wherein the controller is configured to vary the angle of tilt of the tiltable MEMS mirror so as to shift optical frequencies of the wavelength sub-beams by a first frequency shift, upon receiving a corresponding external command.
12. The wavelength selective device of claim 11, wherein the controller comprises a microprocessor coupled to the temperature sensor and configured to receive the external command, and a MEMS driver coupled to the microprocessor, for varying the angle of tilt of the tiltable MEMS mirror.
13. The wavelength selective device of claim 1, wherein in operation, the wavelength drift is 10 pm or less.
14. A method of thermal stabilization of an arrayed waveguide grating including an input slab having an elongate aperture for free-space coupling of an optical beam, and a plurality of output waveguides for outputting wavelength sub-beams of the optical beam, the method comprising:
(a) coupling the optical beam to the elongate aperture of the input slab by
(I) coupling the optical beam to a tiltable MEMS mirror for reflecting the optical beam; and
(II) directing the reflected optical beam to a focusing element for focusing the reflected optical beam into a focal spot on the elongate aperture, so that when the MEMS mirror is tilted by a first angle, the focal spot is displaced by a first displacement along the elongate aperture;
(b) sensing a change of temperature of the arrayed waveguide grating; and
(c) varying the first angle so as to lessen a wavelength drift of the wavelength sub-beams due to the change of temperature sensed in step (b).
15. The method of claim 14, wherein steps (b) and (c) are performed by a controller at a power consumption of 10 mW or less.
16. The method of claim 15, wherein the power consumption is 1 mW or less.
17. The method of claim 14, further comprising
(a1) splitting a portion of the optical beam and directing the portion to a photoelectric generator for conversion into electric power; and
(a2) using the electric power to power a controller for performing steps (b) and (c).
18. The method of claim 17, further comprising
(j) generating powering light at a powering wavelength different from wavelengths of the optical beam; and
(jj) adding the powering light to the optical beam;
wherein steps (i) and (jj) are performed before step (a); and wherein in step (a1), the split portion of the optical beam includes the powering light and is split by a wavelength-selective splitter.
19. The method of claim 14, further comprising
(d) varying the first angle so as to shift optical frequencies of the wavelength sub-beams by a pre-defined amount.
20. The method of claim 19, wherein step (d) is performed upon receiving a command from a remote location.