What is claimed is:
1. A recombinant viral vector capable of expressing a gene in a selected host cell or tissue comprising:
a) at least a portion of the genome of a DNA virus which exhibits tropicity for said selected host cell or tissue, which portion is capable of infection of said selected host cell or tissue; said genome having been modified to have a level of virulence less than the level of virulence present in a wild type virulent strain of the virus from which said vector is derived; and
b) a gene operatively linked thereto wherein said gene is capable of expression in said selected host cell or tissue after infection of said selected host cell or tissue.
2. The recombinant vector of claim 1, wherein said vector further comprises a DNA sequence containing a nonviral initiation site of DNA synthesis operatively linked to said gene for amplification of said gene.
3. The recombinant vector of claim 1, wherein said DNA virus is a double-stranded neurotropic virus, said human gene is the gene for hypoxanthine-guanine phosphoribosyltransferase, and said vector further comprises a promoter sequence of DNA for promoting expression of said gene.
4. The recombinant vector of claim 3, wherein said DNA virus is herpes simplex virus and said vector is synthesized by a process comprising:
a) cloning a fragment containing a herpes virus thymidine kinase promoter into a suitable plasmid;
b) linearizing said plasmid with Bg1 II to obtain plasmid DNA;
c) obtaining a fragment containing human HPRT cDNA, and blunt-ending and ligated said fragment to BamH1 linkers to form a ligatable fragment;
ligating said ligatable fragment to said linear plasmid DNA to form a recombinant plasmid containing a TK promoter-HPRT minigene;
linearizing and recombining said recombinant plasmid with an intact wild-type herpes virus genome to form recombinant viral progeny containing the TK promoter-HPRT minigene.
5. The recombinant vector of claim 3, wherein said portion of said viral genome contains a deletion in a viral gene necessary for replication of said genome.
6. The recombinant vector of claim 3, wherein said DNA sequence containing said nonviral initiation site is of murine origin.
7. A method of viral-mediated gene therapy for the treatment of a selected host organism comprising the steps of:
a) providing at least a portion of a genome of a DNA virus, said portion being capable of infecting cells of said selected host organism;
b) operatively linking a human gene to said portion to form a recombinant viral vector, said gene being capable of expression in said host cell after infection of said cell by said vector;
c) modifying said recombinant viral vector to have a level of virulence less than the level of virulence present in a wild type virulent strain from which said portion of said genome is derived; and
d) directly contacting said selected host organism with sufficient quantity of said viral vector and for a time effective for said viral vector to infect said organism.
8. The method of claim 7, further comprising the step of providing said recombinant vector with a nonviral site of initation of DNA synthesis.
9. The method of claim 8, wherein said portion of said genome of said virus is replication-defective.
10. The method of claim 9, wherein said virus is a double-stranded neurotropic virus and said site of nonviral initiation is contained within as autonomous replicating sequence of murine orgin.
11. The method of claim 10, wherein said virus is a herpes simplex virus, said gene is the gene for hypoxanthine-guanine phosphoribosyltransferase, and said recombinant vector further comprises a viral promoter sequence for promoting expression of said gene.
12. A method for providing means for amplification of a gene carried on a recombinant viral vector comprising the steps of:
a) providing at least a portion of the genome of a virus, said portion being capable of infecting a host organism;
b) operatively linking a human gene to said portion to form a recombinant viral vector, wherein said gene is capable of expression in said host organism after infection of said organism by said vector; and
c) providing a nonviral site of initiation of neuclic acid synthesis for amplification of said gene.
13. The method of claim 12, wherein said method further comprises the step of modifying said portion of said genome of said virus replication-defective.
14. The method of claim 12, wherein said nonviral site of initiation resides on an autonomous replicating sequence of nucleic acids.
15. The method of claim 14, wherein said virus is a double stranded DNA virus which exhibits tissue-tropism, said human gene codes for an enzyme which is selectable in culture, and said autonomous replicating sequence is of murine orgin.
16. The method of claim 15, wherein said virus is herpes simplex virus, said gene is the gene for hypoxanthine-guanine phosphoribosyltransferase and said recombinant vector further comprises a DNA sequence for the herpes simplex thymidine kinase promoter operatively linked thereto.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of designing an integrated circuit, comprising:
receiving a functional description of said integrated circuit;
placing and routing, using a computer, a plurality of synthesized entities to create a physical design implementation for said integrated circuit, wherein each synthesized entity of said plurality of synthesized entities comprises a portion of said functional description of said integrated circuit that has been synthesized into a gate-level implementation; and
manipulating said plurality of synthesized entities to facilitate said physical design implementation satisfying a plurality of design constraints, wherein said manipulating comprises using physical design information of said physical design implementation to ensure satisfying said plurality of design constraints.
2. The method of claim 1, wherein said manipulating said plurality of synthesized entities further comprises:
performing integrated circuit chip level analysis for area, timing and power constraints using aggregate characteristics of said plurality of synthesized entities; and
modifying said plurality of synthesized entities using said integrated circuit chip level analysis to satisfy said design constraints.
3. The method of claim 1, wherein said manipulating said plurality of synthesized entities comprises: merging a first synthesized entity with a second synthesized entity.
4. The method of claim 1, wherein said manipulating said plurality of synthesized entities comprises: splitting synthesized entity into two or more synthesized entities.
5. The method of claim 1, wherein said manipulating said plurality of synthesized entities comprises: moving synthesized entity from one location to another location.
6. The method of claim 1, wherein said manipulating said plurality of synthesized entities comprises: changing size of one or more synthesized entities.
7. The method of claim 1, wherein said manipulating said plurality of synthesized entities comprises: modifying said gate-level implementation of synthesized entity.
8. The method of claim 1, wherein said manipulating said plurality of synthesized entities comprises: resynthesizing said functional description of synthesized entity into a new gate-level implementation.
9. The method of claim 1, further comprising:
providing a global level view of said physical design implementation using said plurality of synthesized entities to enable said global level view, wherein said global level view ensures satisfying said design constraints.
10. A computer-readable storage device comprising a plurality of computer-executable instructions stored therein, said computer-executable instructions comprising:
instructions to receive a functional description of an integrated circuit;
instructions to place and route a plurality of synthesized entities to create a physical design implementation for said integrated circuit, wherein each synthesized entity of said plurality of synthesized entities comprises a portion of said functional description of said integrated circuit that has been synthesized into a gate-level implementation; and
instructions to manipulate said plurality of synthesized entities to facilitate said physical design implementation satisfying a plurality of design constraints, wherein said instructions to manipulate comprise instructions to use physical design information of said physical design implementation to ensure satisfying said plurality of design constraints.
11. The computer-readable storage device of claim 10, wherein said instructions to manipulate said plurality of synthesized entities further comprise:
instructions to perform integrated circuit chip level analysis for area, timing and power constraints using aggregate characteristics of said plurality of synthesized entities;
instructions to modify said plurality of synthesized entities using said integrated circuit chip level analysis to satisfy said design constraints; and
instructions to resynthesize said functional description of synthesized entity into a new gate-level implementation.
12. The computer-readable storage device of claim 10, wherein said instructions to manipulate said plurality of synthesized entities comprise:
instructions to modify said gate-level implementation of synthesized entity.
13. The computer-readable storage device of claim 10, wherein said instructions to manipulate said plurality of synthesized entities comprise:
instructions to merge a first synthesized entity with a second synthesized entity.
14. The computer-readable storage device of claim 10, wherein said instructions to manipulate said plurality of synthesized entities comprise:
instructions to split synthesized entity into two or more synthesized entities.
15. The computer-readable storage device of claim 10, wherein said instructions to manipulate said plurality of synthesized entities comprise:
instructions to move synthesized entity from one location to another location.
16. The computer-readable storage device of claim 10, wherein said instructions to manipulate said plurality of synthesized entities comprise:
instructions to change size of one or more synthesized entities.
17. The computer-readable storage device of claim 10, wherein said computer-executable instructions further comprise:
instructions to provide a global level view of said physical design implementation using said plurality of synthesized entities to enable said global level view, wherein said global level view ensures satisfying said design constraints.
18. An electronic design tool comprising:
a functional description analyzer configured to facilitate partitioning a functional description of an integrated circuit into a plurality of entities based on a plurality of rules; and
an entity engine configured to create and manage a plurality of synthesized entities, wherein each synthesized entity comprises a portion of said functional description of said integrated circuit that has been synthesized into a gate-level implementation.
19. The electronic design tool of claim 18, further comprising: a physical design engine configured to use said synthesized entities to create a physical design implementation for said integrated circuit that meets a plurality of design constraints.
20. The electronic design tool of claim 18, wherein if said design constraints are met, physical design information of said physical design implementation is useable for a final physical design implementation for said integrated circuit.