1. A method for balancing correlated clock networks, the method comprising:
in a correlated clock network including a plurality of clock networks, identifying one or more clock networks of the plurality of clock networks, the one or more clock networks having more active elements as compared to other clock networks of the plurality of clock networks;
for those identified clock networks, identifying a pattern of active elements therein as traversed by a clock signal; and
for those unidentified clock networks in the correlated clock networks, adding active elements such that those added active elements traversed by the clock signal match those traversed in the identified clock networks.
2. The method of claim 1 further comprising setting the added active elements to a state that does not alter the functionality of the correlated clock networks.
3. The method of claim 1 wherein matching of active elements lowers skew between the clock networks in the plurality of correlated clock networks.
4. The method of claim 1 wherein the adding of active elements matches a clock network delay for each of the clock networks in the plurality of correlated clock networks.
5. A method for balancing correlated clock networks, the method comprising:
identifying each clock path within the correlated clock networks that do not have a longest series of non-clock signal delivering logic cells;
for each identified clock path, adding one or more logic cells to the identified clock path until each active element matches each active element in a path with the longest series of non-clock delivering logic cells; and
setting one or more inputs to the added logic cells to a value that will pass a clock signal.
6. The method of claim 5 wherein each clock path matches in propagation delay.
7. A method for preventing clock skew and impedance differences affecting a correlated clock network, the method comprising:
performing a clock balancing for the correlated clock network;
identifying each related node across a sub-network in the correlated clock network;
identifying each input driven via the identified related nodes; and
adding one or more active elements to one or more nodes in the identified related nodes until each element in the identified related nodes drives a same number of inputs.
8. The method of claim 7 wherein the added elements mirror any pre-existing elements in the identified related node.
9. The method of claim 8 wherein the added one or more elements are placed in close proximity to the mirrored pre-existing elements.
10. An apparatus configured for clock balancing, the apparatus comprising:
means in a correlated clock network including a plurality of clock networks, for identifying one or more clock networks of the plurality of clock networks, the one or more clock networks having more active elements as compared to other clock networks of the plurality of clock networks;
for those identified clock networks, means for identifying a pattern of active elements therein as traversed by a clock signal; and
for those unidentified clock networks in the correlated clock networks, means for adding active elements such that those active elements traversed by a clock signal match those traversed in the clock networks with the most active elements.
11. A computer-readable medium containing computer-executable instructions to perform a method for clock balancing, the method comprising:
identifying each clock path within the correlated clock networks that do not have a longest series of non-clock signal delivering logic cells;
for each identified clock path, adding one or more logic cells to the identified clock path until each active element matches each active element in a path with the longest series of non-clock delivering logic cells; and
setting one or more inputs to the added logic cells to a value that will pass a clock signal.
12. The computer-readable medium of claim 11 further comprising computer-executable instructions to perform for each logic cell in the series, setting one or more inputs to non-controlling values.
13. A computer-readable medium containing computer-executable instructions to perform a method for balancing correlated clock networks, the method comprising:
in a correlated clock network including a plurality of clock networks, identifying one or more clock networks of the plurality of clock networks, the one or more clock networks having more active elements as compared to other clock networks of the plurality of clock networks;
for those identified clock networks, identifying a pattern of active elements therein as traversed by a clock signal; and
for those unidentified clock networks in the correlated clock networks, adding active elements such that those added active elements traversed by the clock signal match those traversed in the identified clock networks.
14. The computer-readable medium of claim 13 having further computer-executable instructions for setting active elements added to the plurality of correlated clock networks to a state that allows appropriate clock signals to pass through similarly to those active elements to which the added active elements were added.
15. The computer-readable medium of claim 13 wherein the adding active elements lowers skew between the clock networks in the plurality of correlated clock networks.
16. The computer-readable medium of claim 13 wherein the adding of active elements matches a clock network delay for each of the clock networks in the plurality of correlated clock networks.
17. A computer-readable medium containing computer-executable instructions to perform a method for preventing clock skew and impedance differences affecting a correlated clock network, the method comprising:
performing a clock balancing for the correlated clock network;
identifying any related nodes in the correlated clock network;
identifying any inputs driven via one or more of the identified related nodes; and
adding one or more active elements to each of the identified related nodes until each node of the identified related nodes have same inputs attached thereto.
18. The computer-readable medium of claim 17 wherein the performing a clock balancing includes:
in the correlated clock network including a plurality of clock networks, identifying one or more clock networks of the plurality of clock networks, the one or more clock networks having more active elements as compared to other clock networks of the plurality of clock networks;
for those identified clock networks, identifying a pattern of active elements therein as traversed by a clock signal; and
for those unidentified clock networks in the correlated clock networks, adding active elements such that those added active elements traversed by the clock signal match those traversed in the identified clock networks.
19. A network synthesis tool for preventing clock skew and impedance differences affecting a correlated clock network, the network synthesis tool comprising:
a clock balancing module to clock balance the correlated clock network;
a node identification module to identify any related nodes across a sub-network in the correlated clock network;
an input identification module to identify each input driven via the identified related nodes; and
an element insertion module to add one or more active elements to one or more nodes in the identified related nodes until each element in the identified related nodes drives a same number of inputs.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of manufacturing a semiconductor integrated circuit, the method comprising:
providing measurements of degradation in lithography processing of a projection imaging tool;
adjusting operation of the projection imaging tool in response to the measurements; and
exposing a substrate using the adjusted projection imaging tool for a semiconductor integrated circuit manufacturing process.
2. A method as defined in claim 1, wherein the degradation comprises lens aberrations.
3. A method as defined in claim 1, wherein the degradation comprises illumination source variation.
4. A method as defined in claim 1, wherein the degradation comprises variation in transmission as a function of transverse ray direction.
5. A method as defined in claim 1, wherein the degradation comprises scan synchronization error.
6. A method as defined in claim 1, wherein the degradation comprises lens distortion in a dynamically scanned field.
7. A method as defined in claim 1, wherein the degradation comprises static lens distortion.
8. A method as defined in claim 1, wherein the degradation comprises static lens field curvature as a function of field position.
9. A method as defined in claim 1, wherein the degradation comprises dynamic lens field curvature as a function of cross scan direction field position.
10. A method as defined in claim 1, wherein the degradation comprises dynamic height and roll error as a function of scan position.
11. A method as defined in claim 1, wherein the degradation comprises wafer stage grid and yaw error.
12. A method as defined in claim 1, wherein adjusting the operation of the projection imaging tool comprises adjusting the projection imaging tool in a single adjustment.
13. A method as defined in claim 1, wherein adjusting the operation of the projection imaging tool comprises adjusting the projection imaging tool in a series of sub-adjustments.
14. A method as defined in claim 1, further comprising adjusting multiple projection imaging tools.
15. A method as defined in claim 1, wherein the measurements are made using in-situ metrology tests.
16. A projection imaging tool comprising:
a wafer stage;
a controller configured to receive measurements of degradation in lithography processing of the projection imaging tool and to adjust operation of the projection imaging tool in response to the received measurements, wherein the adjusted projection imaging tool is used to expose a substrate at the wafer stage.
17. A projection imaging tool as defined in claim 16, wherein the degradation comprises lens aberrations.
18. A projection imaging tool as defined in claim 16, wherein the degradation comprises illumination source variation.
19. A projection imaging tool as defined in claim 16, wherein the degradation comprises variation in transmission as a function of transverse ray direction.
20. A projection imaging tool as defined in claim 16, wherein the degradation comprises scan synchronization error.
21. A projection imaging tool as defined in claim 16, wherein the degradation comprises lens distortion in a dynamically scanned field.
22. A projection imaging tool as defined in claim 16, wherein the degradation comprises static lens distortion.
23. A projection imaging tool as defined in claim 16, wherein the degradation comprises static lens field curvature as a function of field position.
24. A projection imaging tool as defined in claim 16, wherein the degradation comprises dynamic lens field curvature as a function of cross scan direction field position.
25. A projection imaging tool as defined in claim 16, wherein the degradation comprises dynamic height and roll error as a function of scan position.
26. A projection imaging tool as defined in claim 16, wherein the degradation comprises wafer stage grid and yaw error.
27. A projection imaging tool as defined in claim 16, wherein adjusting the operation of the projection imaging tool comprises adjusting the projection imaging tool in a single adjustment.
28. A projection imaging tool as defined in claim 16, wherein adjusting the operation of the projection imaging tool comprises adjusting the projection imaging tool in a series of sub-adjustments.
29. A projection imaging tool as defined in claim 16, further comprising adjusting multiple projection imaging tools.
30. A projection imaging tool as defined in claim 16, wherein the measurements are made using in-situ metrology tests.
31. A projection imaging tool comprising:
means for receiving measurements of degradation in a lithography processing of the projection imaging tool;
means for adjusting operation of the projection imaging tool in response to the received measurements; and
means for exposing a substrate using the adjusted projection imaging tool.
32. A method of semiconductor manufacture, the method comprising:
emulating a projection imaging machine utilizing a database comprising historical and current machine states;
evaluating the projection imaging machine process capability; and
determining if the machine needs adjustment and, if it does need adjustment, then determining what adjustments are desired.
33. A method as defined in claim 32, wherein adjustment of the projection imaging machine comprise adjusting the projection imaging machine in a single adjustment.
34. A method as defined in claim 32, wherein adjustment of the projection imaging machine comprises adjusting the projection imaging machine in a series of sub-adjustments.
35. A method of semiconductor manufacture, the method comprising:
emulating a plurality of projection imaging machines utilizing a database comprising historical and current states of the machines;
evaluating machine-to-machine processing capabilities; and
determining if any of the machines need adjustment and, if any machines need adjustment, then determining what adjustments are desired.
36. A method as defined in claim 35, wherein adjusting one of the plurality of projection imaging machines comprise adjusting the projection imaging machine in a single adjustment.
37. A method as defined in claim 35, wherein adjusting one of the plurality of projection imaging machines comprises adjusting the projection imaging machine in a series of sub-adjustments.
38. A method as defined in claim 35, wherein adjusting projection imaging machines comprises adjusting a set of machines in a single step and adjusting other machines in a series of sub-adjustments.
39. A method as defined in claim 38, wherein the set of machines adjusted in a single step comprise machines that have been offline.
40. A method as defined in claim 38, wherein the set of machines adjusted in a single step comprises new machines.