1. A method for manufacturing a color liquid crystal panel, said color liquid crystal panel having plural pixels, each having a thin film transistor therein, a reflective electrode connected to said thin film transistor, and a transparent electrode,
said color liquid crystal panel being constructed such that a display surface of said color liquid crystal panel allows a light emitted from a backlight to exit from said display surface through said transparent electrode and another light inputted to said display surface to exit from said display surface after being reflected by said reflective electrode,
said method for manufacturing said color liquid crystal panel comprising the steps of:
preparing a photomask in such a manner that at least one opening is formed in said photomask so as to vary an area of said at least one opening depending on a color to be displayed; and
forming a pattern in a raw material film constituting said color filter by using said photomask to make said color filter have at least one opening varying depending on a color to be displayed in a part thereof facing said reflective electrode, the at least one opening in said color filter having an area that is no more than 40% of an area of said reflective electrode.
2. The method for manufacturing a color liquid crystal panel according to claim 1, further having a step of forming a transparent film covering all color filters formed corresponding to colors to be displayed and a step of flattening said transparent film after a step of forming said color filter.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor device comprising:
a first wiring;
a second wiring;
a third wiring;
a fourth wiring; and
a fifth wiring,
wherein a plurality of memory elements are supported by a substrate including a semiconductor material, and connected in series between the first wiring and the second wiring, each memory element comprising:
a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode;
a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode; and
a third transistor comprising a third gate electrode, a third source electrode, and a third drain electrode,
wherein the second transistor includes an oxide semiconductor layer,
wherein the first gate electrode and one of the second source electrode and the second drain electrode are electrically connected to each other,
wherein the first wiring, the first source electrode, and the third source electrode are electrically connected to each other,
wherein the second wiring, the first drain electrode, and the third drain electrode are electrically connected to each other,
wherein the third wiring and the other of the second source electrode and the second drain electrode are electrically connected to each other,
wherein the fourth wiring and the second gate electrode are electrically connected to each other, and
wherein the fifth wiring and the third gate electrode are electrically connected to each other.
2. The semiconductor device according to claim 1 further comprising:
a sixth wiring;
a seventh wiring;
a fourth transistor with a gate electrode electrically connected to the sixth wiring; and
a fifth transistor with a gate electrode electrically connected to the seventh wiring,
wherein the second wiring is electrically connected to the first drain electrode and the third drain electrode through the fourth transistor, and
wherein the first wiring is electrically connected to the first source electrode and the third source electrode through the fifth transistor.
3. A semiconductor device comprising:
a first wiring;
a second wiring;
a third wiring;
a fourth wiring; and
a fifth wiring,
wherein a plurality of memory elements are supported by a substrate including a semiconductor material, and connected in series between the first wiring and the second wiring, each memory element comprising:
a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode;
a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode; and
a capacitor,
wherein the second transistor includes an oxide semiconductor layer,
wherein the first gate electrode, one of the second source electrode and the second drain electrode, and one electrode of the capacitor are electrically connected to each other,
wherein the first wiring and the first source electrode are electrically connected to each other,
wherein the second wiring and the first drain electrode are electrically connected to each other,
wherein the third wiring and the other of the second source electrode and the second drain electrode are electrically connected to each other,
wherein the fourth wiring and the second gate electrode are electrically connected to each other, and
wherein the fifth wiring and another electrode of the capacitor are electrically connected to each other.
4. The semiconductor device according to claim 3 further comprising:
a sixth wiring;
a seventh wiring;
a fourth transistor with a gate electrode electrically connected to the sixth wiring; and
a fifth transistor with a gate electrode electrically connected to the seventh wiring,
wherein the second wiring is electrically connected to the first drain electrode through the fourth transistor, and
wherein the first wiring is electrically connected to the first source electrode through the fifth transistor.
5. The semiconductor device according to claim 1, wherein the second transistor comprises the second gate electrode over the substrate including the semiconductor material, a second gate insulating layer over the second gate electrode, the oxide semiconductor layer over the second gate insulating layer, and the second source electrode and the second drain electrode electrically connected to the oxide semiconductor layer.
6. The semiconductor device according to claim 3, wherein the second transistor comprises the second gate electrode over the substrate including the semiconductor material, a second gate insulating layer over the second gate electrode, the oxide semiconductor layer over the second gate insulating layer, and the second source electrode and the second drain electrode electrically connected to the oxide semiconductor layer.
7. The semiconductor device according to claim 1, wherein the first transistor comprises a channel formation region provided in the substrate including the semiconductor material, at least a first impurity region and a second impurity region between which is provided the channel formation region, a first gate insulating layer over the channel formation region, the first gate electrode being located over the first gate insulating layer, and the first source electrode being electrically connected to one of the first impurity region and the second impurity region, and the first drain electrode being electrically connected to the other one of the first impurity region and the second impurity region.
8. The semiconductor device according to claim 3, wherein the first transistor comprises a channel formation region provided in the substrate including the semiconductor material, at least a first impurity region and a second impurity region between which is provided the channel formation region, a first gate insulating layer over the channel formation region, the first gate electrode being located over the first gate insulating layer, and the first source electrode being electrically connected to one of the first impurity region and the second impurity region, and the first drain electrode being electrically connected to the other one of the first impurity region and the second impurity region.
9. The semiconductor device according to claim 1 wherein the third transistor comprises a channel formation region provided in the substrate including the semiconductor material, at least a first impurity region and a second impurity region between which is provided the channel formation region, a third gate insulating layer over the channel formation region, the third gate electrode being located over the third gate insulating layer, the third source electrode being electrically connected to one of the first impurity region and the second impurity region, and the third drain electrode being electrically connected to the other one of the first impurity region and the second impurity region.
10. The semiconductor device according to claim 1, wherein the substrate including the semiconductor material is a single crystal semiconductor substrate or an SOI substrate.
11. The semiconductor device according to claim 3, wherein the substrate including the semiconductor material is a single crystal semiconductor substrate or an SOI substrate.
12. The semiconductor device according to claim 1, wherein the semiconductor material is silicon.
13. The semiconductor device according to claim 3, wherein the semiconductor material is silicon.
14. The semiconductor device according to claim 1, wherein the oxide semiconductor layer includes an In\u2014Ga\u2014Zn\u2014O-based oxide semiconductor material.
15. The semiconductor device according to claim 3, wherein the oxide semiconductor layer includes an In\u2014Ga\u2014Zn\u2014O-based oxide semiconductor material.
16. The semiconductor device according to claim 1, wherein the oxide semiconductor layer includes a crystal of In2Ga2ZnO7.
17. The semiconductor device according to claim 3, wherein the oxide semiconductor layer includes a crystal of In2Ga2ZnO7.
18. The semiconductor device according to claim 1, wherein a concentration of hydrogen of the oxide semiconductor layer is 5\xd71019 atomscm3 or less.
19. The semiconductor device according to claim 3, wherein a concentration of hydrogen of the oxide semiconductor layer is 5\xd71019 atomscm3 or less.
20. The semiconductor device according to claim 1, wherein an off-state current of the second transistor is 1\xd710\u221213 A or less.
21. The semiconductor device according to claim 3, wherein an off-state current of the second transistor is 1\xd710\u221213 A or less.
22. A semiconductor device comprising:
a first wiring;
a second wiring;
a third wiring;
a fourth wiring; and
a fifth wiring,
wherein a plurality of memory elements are supported by a substrate including a semiconductor material, and connected in series between the first wiring and the second wiring, each memory element comprising:
a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode;
a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode; and
a third transistor comprising a third gate electrode, a third source electrode, and a third drain electrode,
wherein the first gate electrode and one of the second source electrode and the second drain electrode are electrically connected to each other,
wherein the first wiring, the first source electrode, and the third source electrode are electrically connected to each other,
wherein the second wiring, the first drain electrode, and the third drain electrode are electrically connected to each other,
wherein the third wiring and the other of the second source electrode and the second drain electrode are electrically connected to each other,
wherein the fourth wiring and the second gate electrode are electrically connected to each other, and
wherein the fifth wiring and the third gate electrode are electrically connected to each other.
23. A semiconductor device comprising:
a first wiring;
a second wiring;
a third wiring;
a fourth wiring; and
a fifth wiring,
wherein a plurality of memory elements are supported by a substrate including a semiconductor material, and connected in series between the first wiring and the second wiring, each memory element comprising:
a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode;
a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode; and
a capacitor,
wherein the first gate electrode, one of the second source electrode and the second drain electrode, and one electrode of the capacitor are electrically connected to each other,
wherein the first wiring and the first source electrode are electrically connected to each other,
wherein the second wiring and the first drain electrode are electrically connected to each other,
wherein the third wiring and the other of the second source electrode and the second drain electrode are electrically connected to each other,
wherein the fourth wiring and the second gate electrode are electrically connected to each other, and
wherein the fifth wiring and another electrode of the capacitor are electrically connected to each other.