What is claimed is:
1. A method of making a semiconductor device comprising:
forming a conductive layer that contacts a via, wherein the conductive layer includes a sufficient amount of a dopant, which will diffuse in the direction that is opposite to the direction in which electrons will flow through the conductive layer, to reduce the electromigration of the material that comprises the bulk of the conductive layer without significantly increasing the conductive layer’s resistance.
2. The method of claim 1 wherein the dopant has a positive effective valence.
3. The method of claim 2 wherein the dopant is selected from the group consisting of iron, platinum, zirconium, and cobalt.
4. The method of claim 1 wherein the dopant is included in the conductive layer at a concentration of between about 0.1 atomic % and about 10 atomic %.
5. The method of claim 1 wherein the conductive layer is positioned on top of the via.
6. The method of claim 1 wherein the via is positioned on top of the conductive layer.
7. The method of claim 1 wherein the conductive layer comprises copper.
8. The method of claim 1 wherein the conductive layer includes a second dopant that will diffuse in the same direction as electrons will flow through the conductive layer.
9. The method of claim 8 wherein the second dopant has a negative effective valence.
10. The method of claim 8 wherein the second dopant is selected from the group consisting of aluminum, cadmium, magnesium and tin.
11. A method of making a semiconductor device comprising:
forming on a substrate a conductive layer that includes a sufficient amount of a dopant, which will diffuse in the direction that is opposite to the direction in which electrons will flow through the conductive layer, to reduce the electromigration of the material that comprises the bulk of the conductive layer without significantly increasing the conductive layer’s resistance; then
forming a dielectric layer on the conductive layer;
etching a via through the dielectric layer; and
filling the via with a conductive material.
12. The method of claim 11 further comprising:
forming a barrier layer on the conductive layer;
forming the dielectric layer on the barrier layer;
etching the via through a portion of the barrier layer, after etching the via through the dielectric layer, to expose a portion of the conductive layer; and then
filling the via with the conductive material.
13. The method of claim 12 wherein the conductive layer comprises copper, the dopant is selected from the group consisting of iron, platinum, zirconium, and cobalt, and the dopant is introduced into the conductive layer after the conductive layer is formed on the substrate.
14. The method of claim 13 wherein the dopant is introduced into the conductive layer by ion implanting the dopant into that layer, and wherein the dopant is included in the conductive layer at a concentration of between about 0.1 atomic % and about 10 atomic %.
15. The method of claim 12 wherein the conductive layer comprises copper and wherein the dopant is integrated into the conductive layer by adding the dopant to a seed layer, then forming the conductive layer on the seed layer.
16. The method of claim 11 wherein the conductive layer includes a second dopant that will diffuse in the same direction as electrons will flow through the conductive layer.
17. The method of claim 16 wherein the second dopant has a negative effective valence.
18. The method of claim 16 wherein the second dopant is selected from the group consisting of aluminum, cadmium, magnesium and tin.
19. A method of making a semiconductor device comprising:
forming a dielectric layer on a substrate;
etching a via through the dielectric layer and a trench into the dielectric layer; and
filling the via and trench with a conductive layer that includes a sufficient amount of a dopant, which will diffuse in the direction that is opposite to the direction in which electrons will flow through the conductive layer, to reduce the electromigration of the material that comprises the bulk of the conductive layer without significantly increasing the conductive layer’s resistance.
20. The method of claim 19 wherein the conductive layer comprises copper, and the dopant is introduced into the conductive layer, after the conductive layer fills the via and trench, by ion implanting the dopant into that layer.
21. The method of claim 20 wherein the dopant is selected from the group consisting of iron, platinum, zirconium, and cobalt, and wherein the dopant is included in the conductive layer at a concentration of between about 0.1 atomic % and about 10 atomic %.
22. The method of claim 19 wherein the conductive layer includes a second dopant that will diffuse in the same direction as electrons will flow through the conductive layer.
23. The method of claim 22 wherein the second dopant has a negative effective valence.
24. The method of claim 22 wherein the second dopant is selected from the group consisting of aluminum, cadmium, magnesium and tin.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A computer implemented method for a discrete-clock computer system having a plurality of processors comprising:
receiving an activity comprising at least one of: a constraint for a thread in the activity specifying a desired earliest start time, amount of requested execution time, and a deadline; and a reservation for the activity specifying a recurring desired number of time units within a desired period;
determining one of the plurality of processors for which execution of the activity and threads within the activity that are to be scheduled, based on a heuristic; modifying at least one of:
the desired earliest start time, the amount of requested execution time and the deadline for the time constraint, and the desired amount of execution and the desired period of the reservation based on a granularity of the discrete-clock computer system; and
when the computer system has a modifiable period, the modifiable period based on at least one of the earliest start time, the amount of requested execution time and the deadline for a time constraint, and the desired amount of execution and the desired period of the reservation; and
scheduling the activity and the constraint for execution on the determined one of the plurality of processors, including inserting the activity and the constraint on a schedule for the determined one of the plurality of processors.
2. The method of claim 1, wherein the heuristic comprises determining the least loaded of the plurality of processors.
3. The method of claim 1, wherein the heuristic comprises determining a processor having other activities scheduled for execution thereon that are related to the activity.
4. The method of claim 1, wherein the heuristic comprises determining a processor having other activities scheduled for execution thereon that have a similar period to the desired period.
5. The method of claim 1, wherein the heuristic comprises randomly selecting a processor.
6. The method of claim 1, wherein the heuristic comprises performing an exhaustive search.
7. The method of claim 1, wherein the schedule is specific to the determined one of the plurality of processors.
8. The method of claim 1, wherein the schedule is specific to a sub-plurality of the processors including the determined one of the plurality of processors.
9. The method of claim 1, wherein the schedule is for all the plurality of processors including the determined one of the plurality of processors.
10. The method of claim 1, wherein the computer system has an existing scheduler, and wherein the scheduling is performed utilizing the existing scheduler.
11. The method of claim 10, wherein the existing scheduler uses unreserved time slots to schedule otherwise unscheduled threads.
12. The method of claim 11, wherein the existing scheduler also schedules scheduled threads during unreserved time slots.
13. A computer implemented method for a discrete-clock computer system having a plurality of processors comprising:
receiving an activity comprising at least one of: a constraint for a thread in the activity specifying a desired earliest start time, an amount of requested execution time, and a deadline; and a reservation for the activity specifying a recurring desired number of time units within a desired period;
determining at least one of the plurality of processors for which execution of the activity and threads within the activity that are to be scheduled, based on a heuristic;
modifying at least one of:
the desired earliest start time, the amount of requested execution time and the deadline for the time constraint, and the desired amount of execution and the desired period of the reservation based on a granularity of the discrete-clock computer system; and
when the computer system has a modifiable period, the modifiable period based on at least one of the earliest start time, the amount of requested execution time and the deadline for a time constraint, and the desired amount of execution and the desired period of the reservation; and
scheduling the activity and the constraint for execution on the determined one of the plurality of processors, including inserting the activity and the constraint on a schedule for the determined at least one of the plurality of processors.
14. The method of claim 13, wherein determining at least one of the plurality of processors comprises determining a single one of the plurality of processors.
15. The method of claim 13, wherein determining at least one of the plurality of processors comprises determining whether the activity fits on a single one of the plurality of processors, and upon determining that the activity does not fit on a single one of the plurality of processors, splitting the activity onto at least two of the plurality of processors.