1. An electronic circuit including a first semiconductor device and a second semiconductor device on a mounting substrate, wherein
the first semiconductor device includes external terminals of a plurality of bits,
the second semiconductor device includes external terminals of a plurality of bits, a semiconductor chip having a plurality of connecting electrodes, and assembling lines which connect the external terminals of a plurality of bits and the plurality of connecting electrodes of the semiconductor chip of the second semiconductor device,
the mounting substrate includes a plurality of mounting substrate lines which are connected in common with external terminals of a plurality of bits of the first semiconductor device and external terminals of a plurality of bits of the second semiconductor device for every bit,
the mounting substrate lines have lengths thereof from the external terminals of the first semiconductor device to the external terminals of the second semiconductor device made unequal for respective bits,
the assembling lines of the second semiconductor device have made lengths thereof unequal for respective bits, and
the unequal lengths of the mounting substrate lines have a relationship which offsets the unequal lengths of the assembling lines.
2. An electronic circuit according to claim 1, wherein the first semiconductor device is formed of a synchronous memory, the second semiconductor device is formed of a data processor which is capable of getting access to and controlling the synchronous memory, and the data processor performs parallel inputtingoutputting of access data of a plurality of bits between the data processor and the synchronous memory via the mounting substrate lines.
3. An electronic circuit according to claim 2, wherein the external terminal of a plurality of bits of the synchronous memory has data inputtingoutputting timing thereof synchronized with the clock signal, and the data processor acquires data outputted from the synchronous memory in synchronism with the clock signal which is outputted from the synchronous memory.
4. An electronic circuit according to claim 3, wherein the second semiconductor device includes the package structure in which a large number of solder ball electrodes are annularly formed on the package substrate in a plurality of rows as external terminals, wherein unequal lengths of the assembling lines in the inside of the package substrate have the difference integer times as large as a pitch in the row direction of the solder ball electrode.
5. An electronic circuit according to claim 1, wherein the first semiconductor device has lengths of the assembling lines thereof from the external terminals thereof to connection electrodes of the semiconductor chip made equal to each other.
6. An electronic circuit including a first semiconductor device and a second semiconductor device on a mounting substrate, wherein
the first semiconductor device includes external terminals of a plurality of bits,
the second semiconductor device includes external terminals of a plurality of bits, a semiconductor chip having a plurality of connecting electrodes, and assembling lines which connect the external terminals of a plurality of bits and the plurality of connecting electrodes of the semiconductor chip of the second semiconductor device,
the mounting substrate includes a plurality of mounting substrate lines which are connected in common with external terminals of a plurality of bits of the first semiconductor device and external terminals of a plurality of bits of the second semiconductor device for every bit,
the mounting substrate lines have lengths thereof from the external terminals of the first semiconductor device to the external terminals of the second semiconductor device made unequal for respective bits,
the assembling lines of the second semiconductor device have made lengths thereof unequal for respective bits, and
the unequal lengths of the mounting substrate lines have a relationship which offsets the unequal lengths of the assembling lines.
7. A semiconductor device according to claim 6, wherein
the semiconductor chip includes a determination circuit which performs a determination operation using a reference potential supplied from a predetermined pad electrode,
the package substrate includes a first conductive layer which is used for the connection with the pad electrodes of the semiconductor chip, a second conductive layer which is used as a ground plane, a third conductive layer which is used as a power source plane, and a fourth conductive layer which is used for the connection with the mounting substrate, and
the third conductive layer includes a power source plane which is connected with the determination circuit and lines for the reference potential, wherein the lines for the reference potential are arranged in a state that the lines for the reference potential are surrounded by the power source plane.
8. An electronic circuit according to claim 7, wherein
the ground plane and the power source plane include specified regions where via holes or through holes are not formed in a penetrating manner with a width equal to or larger than one pitch of external terminals which are arranged on the semiconductor device.
9. An electronic circuit according to claim 8, wherein the first semiconductor device is constituted of a plurality of semiconductor memory devices, and the second semiconductor device is a semiconductor control device which is capable of getting access to and controlling the semiconductor memory devices, wherein
the mounting substrate includes a power source plane of a terminating power source for terminating lines which connect the semiconductor memory devices and the semiconductor control device by way of terminating resistances,
the semiconductor memory devices are mounted closer to the power source plane of the terminating power source than the semiconductor control device,
to the power source plane of the terminating power source, terminating resistances which are connected with the lines and a plurality of first stabilizing capacities which are arranged close to the terminating resistances are connected in a dispersed manner, and
a second stabilizing capacity which is larger than the first stabilizing capacities is connected to an end portion of the power source plane remote from the supply end which supplies the terminating power source.
10. An electronic circuit according to claim 9, wherein among the lines, the one-way lines having a branch to which a plurality of semiconductor memory devices are connected in common, include lines which have terminating resistances thereof joined to the route having the longer route length starting from the semiconductor control device and lines which have terminating resistances thereof joined to the shorter route in mixture, and
a maximum value of the difference of the route length between the longer route in the one-way line which has the terminating resistance thereof joined to the shorter route and the shorter route is set to a minimum value or less of the difference of the route length between the shorter route in the one-way line which has the terminating resistance thereof joined to the longer route and the longer route.
11. An electronic circuit according to claim 10, wherein
the semiconductor control device includes a semiconductor chip mounted on a package substrate,
the semiconductor chip includes a phase locked loop circuit or a delay locked loop circuit,
the first conductive layer of the package substrate is used for connection with pad electrodes of the semiconductor chip, and
the first conductive layer includes a power source line which supplies a power source to the phase locked loop circuit or the delay locked loop circuit, and clock lines which supply clock signals to the phase locked loop circuit or the delay locked loop circuit, wherein the power source line and the clock line are spaced apart from each other with a distance larger than a minimum distance size of lines in the first conductive layer.
12. An electronic circuit according to claim 11, wherein
the semiconductor chip includes converters of either one or both of a digital analog converter and an analog digital converter,
on the third conductive layer, power source planes for the converters are separated from the power source plane for other circuits, and
on the first conductive layer, signal lines for converters are formed at positions where the signal lines for converters are overlapped to the power source plane for the converters.
13. An electronic circuit according to claim 12, wherein
the digital analogue converter includes a circuit which adds a constant current from the constant current source circuit to an output node using a switch,
the semiconductor chip includes a first analog power source terminal and a first analog ground terminal for the constant current source circuit and a second analog power source terminal and a second analog ground terminal for the switch control circuit respectively in a separated manner,
the first analog ground terminal and the second analog ground terminal are connected to analog grounding lines which are separately formed on the first conductive layer, and the respective analog ground lines are connected to the ground plane of the second conductive layer in common, and
the first analog power source terminal and the second analog power source terminal are separately connected to terminals of the fourth conductive layer from the respectively intrinsic analog power source lines which are formed on the first conductive layer via the respective power source planes.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. Use of optically active polymers of N-acryloyl-S-phenylalanine d-neomenthylamide or of the enantiomer thereof as such, in crosslinked form andor in carrier-bonded form as stationary phases for the chromatographic separation of enantiomers of lactones of the general formula (I)
4
wherein
R represents an organic radical and
X represents CH2CH2 or CHCH:
2. Use of optically active polymers according to claim 1 for the chromatographic separation of enantiomers of a lactone chosen from the group consisting of:
5
3. Use of optically active polymers according to claim 1 for the chromatographic separation of enantiomers of ()-trans-(E)-6-2-(2,6-diisopropyl4-(4-fluorophenyl)-3-methoxymethyl-pyrid-5-yl)-ethenyl-3,4,5,6-tetrahydro-4-hydroxy-2H-pyran-2-one.
4. Use of optically active polymers according to claim 1, characterized in that the optically active polymer is employed in a form bonded to silica gel.
5. Use of optically active polymers according to claim 4, characterized in that the optically active polymer is bonded via the mercapto groups from a correspondingly modified silica gel.
6. Process for the chromatographic separation of enantiomers of lactones of the general formula (I) according to claim 1, characterized in that the enantiomer mixture is separated into the enantiomers by means of an optically active polymer of N-acryloyl-S-phenylalanine d-neomenthylamide or of the enantiomer thereof as the chiral stationary phase, using a suitable mobile phase, the optically active polymer being employed as such, in crosslinked form andor in carrier-bonded form.
7. Process according to claim 6, characterized in that a mixture of toluene and tetrahydrofuran is used as the mobile phase.
8. Process according to claim 6, characterized in that the optically active polymer is employed as the stationary phase in a form bonded to silica gel.