1. A cyclic digital to analog converter (CDAC) in a pipeline structure, the CDAC comprising:
a first CDAC block which receives a first digital signal and converts the first digital signal to a first analog value, the first CDAC block comprising a charging capacitor for charging according to the first digital signal and a first storing capacitor for storing the first analog value; and
a second CDAC block which receives a second digital signal and converts the second digital signal to a second analog value, the second CDAC block comprising the charging capacitor for charging according to the second digital signal and a second storing capacitor for storing the second analog value;
wherein the first CDAC block and the second CDAC block share the charging capacitor.
2. The CDAC of claim 1, wherein the first digital signal and the second digital signal are consecutively received.
3. The CDAC of claim 2, wherein the second CDAC block outputs the second analog value while the first CDAC block receives the first digital signal and calculates the first analog value, or the first CDAC block outputs the first analog value while the second CDAC block receives the second digital signal and calculates the second analog value.
4. The CDAC of claim 1, further comprising:
an amplifier which receives, amplifies and outputs a reference voltage signal and at least one of the first analog value and the second analog value output from the first CDAC block and the second CDAC block, respectively.
5. The CDAC of claim 4, further comprising:
a plurality of switches respectively connecting the first CDAC block and the second CDAC block to an output terminal of the amplifier, the plurality of switches being turned on or turned off in response to a corresponding plurality of switching control signals.
6. The CDAC of claim 4, further comprising:
an input unit connected to the charging capacitor, the input unit receiving the first digital signal and the second digital signal and sending the received first digital signal and the second digital signal to the first CDAC block and the second CDAC block, respectively, each of the first digital signal and the second digital signal comprising one of a logic high level or a logic low level.
7. The CDAC of claim 4, wherein the charging capacitor is connected between a first node, which receives the first digital signal and the second digital signal, and a sixth node, which is an input terminal of the amplifier.
8. The CDAC of claim 7, wherein the first CDAC block further comprises:
an eighth switch connected between the sixth node and the first storing capacitor, the eighth switch being turned on or off in response to an eighth switching control signal
a fourth switch connected between the first node and the first storing capacitor, the fourth switch being turned on or off in response to a fourth switching control signal; and
a sixth switch connected between the first storing capacitor and a second input terminal of the amplifier, the sixth switch being turned on or off in response to a sixth switching control signal.
9. The CDAC of claim 8, wherein the first input terminal of the amplifier receives a reference voltage, which has a value within an operation voltage range of the amplifier.
10. The CDAC of claim 9, wherein the reference voltage value comprises an intermediate value of the operation voltage range.
11. The CDAC of claim 9, wherein the second CDAC block comprises:
a seventh switch connected between the sixth node and the second storing capacitor, the seventh switch being turned on or off in response to a seventh switching control signal;
a third switch connected between the first node and the second storing capacitor, the third switch being turned on or off in response to a third switching control signal; and
a fifth switch connected between the seventh switch and the second input terminal of the amplifier, the fifth switch being turned on or off in response to a fifth switching control signal.
12. The CDAC of claim 11, further comprising:
a ninth switch connected between the second storing capacitor and an output terminal of the amplifier, the ninth switch comprising an output node of the second CDAC block; and
a tenth switch connected between the first storing capacitor and the output terminal of the amplifier, the tenth switch comprising an output node of the first CDAC block.
13. The CDAC of claim 6, wherein the input unit comprises:
a first switch connected between a low voltage level signal source and the charging capacitor, the first switch being turned on or off in response to a first switching control signal; and
a second switch connected between a high voltage level signal source and the charging capacitor, the second switch being turned on or off in response to a second switching control signal.
14. The CDAC of claim 12, wherein the third through tenth switching control signals are supplied from an LCD controller or are individually input, and respectively regulate the third through tenth switches according to an operation status of the CDAC.
15. The CDAC of claim 12, wherein each of the third through tenth switches comprises one of an NMOS transistor or a PMOS transistor.
16. The CDAC of claim 12, wherein each of the third through tenth switches comprises a transmission gate.
17. The CDAC of claim 15, wherein the fifth, sixth and eighth switches comprise identical MOS transistors.
18. The CDAC of claim 16, wherein the fifth, sixth and eighth switches comprise identical transmission gates.
19. The CDAC of claim 8, wherein the first CDAC block further comprises:
an eleventh switch connected between the charging capacitor and the sixth node, wherein the eleventh switch is regulated to be always turned on while the CDAC operates.
20. A cyclic digital to analog converter (CDAC) in a pipeline structure, the CDAC comprising:
a first CDAC block which receives a first digital signal and converts the first digital signal to a first analog value;
a second CDAC block which receives a second digital signal and converts the second digital signal to a second analog value; and
an amplifier connectable to the first CDAC block and the second CDAC block, the amplifier receiving the first analog value from the first CDAC block and the second analog value from the second CDAC block through an input terminal and outputting an amplified analog value by differentially amplifying the received first analog value or the received second analog value with a reference voltage,
wherein the first CDAC block comprises:
a first capacitor comprising one terminal that receives the first digital signal and an other terminal connected to a sixth node, which receives the reference voltage, the first capacitor charging according to the first digital signal;
a fourth switch comprising one terminal connected to the one terminal of the first capacitor;
a second capacitor comprising one terminal connected to an other terminal of the fourth switch, the second capacitor storing the first analog value;
a sixth switch comprising one terminal connected to an other terminal of the second capacitor and an other terminal connected to the amplifier input terminal; and
an eighth switch comprising one terminal connected to the other terminal of the second capacitor and an other terminal connected to the sixth node; and
wherein the second CDAC block comprises:
the first capacitor, which receives the second digital signal and charges according to the second digital signal;
a third switch comprising one terminal connected to the one terminal of the first capacitor;
a third capacitor comprising one terminal connected to an other terminal of the third switch, the third capacitor storing the second analog value;
a fifth switch comprising one terminal connected to an other terminal of the third capacitor and an other terminal connected to the amplifier input terminal; and
a seventh switch comprising one terminal connected to the other terminal of the third capacitor and an other terminal connected to the sixth node.
21. The CDAC of claim 20, further comprising:
a ninth switch comprising one terminal connected to the other of the third switch and an other terminal connected to an output terminal of the amplifier; and
a tenth switch comprising one terminal connected to the other terminal of the fourth switch and an other terminal connected to the output terminal of the amplifier.
22. The CDAC of claim 21, wherein an operation cycle comprises:
a first time interval; and
a second time interval,
wherein the eighth switch is turned off and the tenth switch is turned on during the first time interval, and
the sixth switch is turned on and the fifth switch is turned off during the second time interval.
23. The CDAC of claim 22, wherein the second time interval follows the first time interval.
24. The CDAC of claim 23, wherein a charge injection error occurring when the eighth switch is turned off during the first time interval, is compensated for by charge injection errors respectively occurring when the fifth switch is turned off and the sixth switch is turned on during the second time interval.
25. The CDAC of claim 21, wherein the third through tenth switches are turned on or off in response to third through tenth switching control signals, respectively.
26. The CDAC of claim 25, wherein the third through tenth switching control signals are supplied from an LCD controller or individually input, and respectively regulate the third through tenth switches according to an operation status of the CDAC.
27. The CDAC of claim 23, wherein the fifth and seventh switches are on and the third, fourth, sixth and ninth switches are off during the first time interval.
28. The CDAC of claim 27, wherein the third, fourth and eighth switches are off and the seventh and tenth switches are on during the second time interval.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of providing frame rate converted video comprising:
buffering sequential input video frames received at a first frame rate in a buffer, said input video frames containing blended content comprising: a first content from a first video sequence having a first cadence; and a second content from a second video sequence having a second cadence;
forming interpolated frames, by interpolating at least two of said input video frames in said buffer to form a corresponding interpolated frame for each of said input video frames; and
providing output frames at a second frame rate, by selectively outputting one of said interpolated frames and said frames in said buffer as an output frame, depending on said first cadence so as to reduce video judder in said second content in said output frames.
2. The method of claim 1, wherein said first and second video sequences are field sequences.
3. The method of claim 0, further comprising forming said input video frames from said first and second field sequences by de-interlacing.
4. The method of claim 0, wherein said first and second sequences are 60 Hz field sequences, and said first sequence is derived from a 24 frames per second (fps) film using 3:2 pull-down.
5. The method of claim 1, wherein said input video frames comprise Ck, Ck+1, Ck+2, Ck+3, Ck+4 . . . and said output frames comprise Ck, Fk, Ck+1, Fk+1, Fk+1, Ck+2, Fk+2, Ck+3, Fk+3, Fk+3, . . . wherein each Fi denotes a frame formed by interpolating frames Ci and Ci+1 for i=k, k+1, k+2, . . . .
6. The method of claim 1, wherein said input video frames comprise Ck, Ck+1, Ck+2, Ck+3, Ck+4 . . . and said output frames comprise Fk, Ck+1, Fk+1, Fk+2, Fk+2, Ck+3, Fk+3, Ck+4, Fk+4, Fk+4, . . . wherein each Fi denotes a frame formed by interpolating frames Ci and Ci+1 for i=k, k+1, k+2, . . . .
7. The method of claim 1, wherein said second frame rate is greater than said first frame rate.
8. The method of claim 1, wherein said first video sequence is derived by way of a 3:2 pull-down telecine conversion from a 24 fps cinema source.
9. A method of converting input video frames received at a first rate into output frames provided at a second rate, said input video frames containing a blend of a first and a second video content having a first and a second cadence respectively, said method comprising:
i) detecting said first cadence and said second cadence; and
ii) providing said output frames by selectively interpolating said input video frames based on said first and second cadence so as to reduce judder in said first and second content in said output frames.
10. The method of claim 9, wherein said first cadence is 3:2 pull down.
11. A frame rate converter circuit comprising:
an interpolator for forming interpolated video frames from at least two input video frames, said input video frames received sequentially at a first rate, said input video frames containing: a first and second content formed from two video sequences having a first and a second cadence respectively;
a cadence detector for detecting at least one of said first and second cadence to provide a cadence indicator;
a controller for providing a selection parameter based on said cadence indicator, determined so as to reduce judder in said first and second contents in said output frames; and
an output interface for providing output frames at a second rate by selectively outputting one of said input video frames and said interpolated video frames, in accordance with said selection parameter.
12. The circuit of claim 11, wherein said input video frames comprise Ck, Ck+1, Ck+2, Ck+3, Ck+4 . . . and said output frames comprise Ck, Fk, Ck+1, Fk+1, Fk+1, Ck+2, Fk+2, Ck+3, Fk+3, Fk+3, . . . wherein each Fi denotes a frame formed by interpolating frames Ci and Ci+1 for i=k, k+1, k+2, . . . .
13. The circuit of claim 11, wherein said input video frames comprise Ck, Ck+1, Ck+2, Ck+3, Ck+4 . . . and said output frames comprise Fk, Ck+1, Fk+1, Fk+2, Fk+2, Ck+3, Fk+3, Ck+4, Fk+4, Fk+4, . . . wherein each Fi denotes a frame formed by interpolating frames Ci and Ci+1 for i=k, k+1, k+2, . . . .
14. The circuit of claim 11, wherein said interpolator is a motion compensating interpolator.
15. The circuit of claim 11, further comprising a buffer for buffering said input video frames.
16. The circuit of claim 15, further comprising a second buffer for storing said interpolated frames formed by said interpolator.
17. The circuit of claim 15, wherein said buffer is a first-in first-out buffer and said second buffer is a first-in first-out buffer.
18. The circuit of claim 17, wherein said buffer stores at least four of said input video frames and said second buffer stores at least three of said interpolated video frames.
19. An integrated circuit comprising the circuit of claim 11.
20. A display comprising the integrated circuit of claim 19.