1. A method of power management within a tiled storage device comprising a plurality of tiles for storing values, wherein the storage device comprises an internal network for communicating the values among the tiles, and wherein the tiles include network circuits for interfacing with the internal network, and storage circuits for storing the values, the method comprising:
within the storage device, transferring the values between the tiles according to a movement heuristic over the internal network, wherein the internal network automatically transfers the values according to the movement heuristic to provide vacant storage locations for other values written to the tiled storage device from an external device;
within the tiles, measuring activity levels at the individual tiles, wherein the activity levels are reflective of rate of the transfer of values between the individual tiles and other tiles over the network;
determining, within the individual tiles, whether or not the activity level at the individual tile is greater than or equal to a threshold;
responsive to determining that the activity level at the individual tiles is greater than or equal to the threshold, maintaining the individual tiles in a fully active state, in which the values are written to and retrieved from in the storage circuits, and in which the values stored in the tiles that are in the fully active state are transferred according to the movement heuristic to be stored in next tiles; and
responsive to determining that the activity level at the individual tiles is less than the threshold, placing the storage circuits of individual tiles in a power-saving state, in which the values are not stored in the storage circuits, and maintaining the network circuits in an operational state, whereby the values are communicated through individual tiles that are in the power-saving state, so that the values transferred according to the movement heuristic bypass the tiles that are in the power-saving state without being stored in the tiles that are in the power-saving state.
2. The method of claim 1, wherein the tiles have a linear organization with a head and a tail, and wherein when the individual tiles are in the power-saving state, the individual tiles forward push-in requests to a next tile toward a tail of the tiled storage device.
3. The method of claim 1, further comprising:
sending power management status requests to the individual tiles to query the individual tiles as to whether the determining has determined that the activity of the individual tiles is less than the threshold and therefore the individual tiles are ready to enter the power-saving state; and
sending responses from the individual tiles indicating whether or not they are ready to enter the power-saving state.
4. The method of claim 3, wherein the individual tiles also send messages indicating whether or not they are ready to leave the power-saving state.
5. The method of claim 4, further comprising responsive to receiving a message that a corresponding tile is ready to leave the power-saving state, sending a command to the corresponding tile to leave the power-saving state.
6. The method of claim 1, further comprising:
responsive to receiving a response that a corresponding tile is ready to enter the power-saving state, sending multiple requests to the corresponding tile to push-back dirty values to a backing store interface; and
sending a command to the corresponding tile to enter the power-saving state, and wherein the placing the individual tiles in the power-saving state is further performed only in response to receiving the command.
7. The method of claim 6, further comprising:
subsequent to the sending of the multiple requests to the corresponding tile to push-back dirty values, waiting a predetermined period for the dirty values to enter a push-back queue; and
determining whether the push-back queue has a predetermined number of open entries, and wherein the sending a command is performed only in response to determining that the push-back queue has a predetermined number of open entries after the multiple requests have been sent.
8. The method of claim 1, wherein the activity level at the individual tiles is a corresponding hit rate of the individual tiles and the threshold is a hit threshold.
9. The method of claim 8, wherein the determining further determines whether a corresponding push-back rate at the individual tiles is less than a push-back threshold, and wherein the placing places the individual tiles in the power-saving state only if their corresponding push-back rate is less that the push-back threshold in addition to the corresponding hit rate being less than the hit threshold.
10. The method of claim 1, wherein when the individual tiles are in the power-saving state, the individual tiles further determine whether or not to leave the power-saving state by measuring an activity level of the network circuits in the individual tiles and compare the activity level to an inactivity threshold.
11. The method of claim 10, wherein the activity level at the individual tiles while the individual tiles are in the power-saving state is a corresponding push-back rate of the individual tiles and wherein the inactivity threshold is a push-back threshold.
12. A storage circuit, comprising:
a plurality of storage tiles for storing values, wherein the individual storage tiles comprise one or more storage locations and a control logic for controlling a power management state of the individual storage tiles; and
a network for communicating the values among the tiles according to a movement heuristic, wherein the tiles include network circuits for interfacing with the network, wherein the control logic within the individual tiles measures an activity level at the individual storage tiles, wherein the activity levels are reflective of rate of the transfer of values between the individual tiles and other tiles over the network, wherein the internal network automatically transfers the values according to the movement heuristic to provide vacant storage locations for other values written to the storage circuit from an external device, wherein the control logic compares an activity level at the individual storage tiles to a threshold, maintains the individual storage tiles in a fully active state if their corresponding activity level is greater than or equal to the threshold, and places the individual storage tiles in a power-saving state if their corresponding activity level is less than the threshold, wherein the values stored in the tiles that are in the fully active state are transferred according to the movement heuristic to be stored in next tiles, and wherein the values transferred according to the movement heuristic bypass the tiles that are in the power-saving state without being stored in the tiles that are in the power-saving state.
13. The storage circuit of claim 12, wherein when the individual storage tiles are in the power-saving state, the control logic within the individual storage tiles forward push-in requests to a next tile toward a tail of the tiled storage device.
14. The storage circuit of claim 12, further comprising an interface that sends power management status requests to the individual storage tiles to query the individual tiles as to whether their control logic has determined that the activity of the individual storage tiles is less than the threshold and therefore the individual storage tiles are ready to enter the power-saving state, and wherein the individual storage tiles send responses to the interface indicating whether or not they are ready to enter the power-saving state.
15. The storage circuit of claim 14, wherein the interface, in response to receiving a response indicating that a corresponding storage tile is ready to enter the power-saving state, further sends multiple requests to the corresponding storage tile to push-back dirty values to a push-back interface, and sends a command to the corresponding storage tile to enter the power-saving state, and wherein the control logic of the individual storage tiles only places the individual storage tiles in the power-saving state in response to receiving the command.
16. The storage circuit of claim 15, wherein the interface, subsequent to the sending of the multiple requests to the corresponding storage tile to push-back dirty values, waits a predetermined period for the dirty values to enter a push-back queue, determines whether the push-back queue has a predetermined number of open entries, and wherein the interface sends the command only in response to determining that the push-back queue has a predetermined number of open entries after the multiple requests have been sent.
17. The storage circuit of claim method of claim 14, wherein the individual storage tiles further send responses to the interface indicating whether or not they are ready to leave the power-saving state.
18. The storage circuit of claim 17, wherein the interface, in response to receiving a response that a corresponding storage tile is ready to leave the power-saving state, sends a command to the corresponding storage tile to leave the power-saving state.
19. The storage circuit of claim 12, wherein the activity level at the individual storage tiles is a corresponding hit rate of the individual storage tiles and the threshold is a hit threshold.
20. The storage circuit of claim 19, wherein the determining further determines whether a corresponding push-back rate at the individual storage tiles is less than a push-back threshold, and wherein the control logic places the individual storage tiles in the power-saving state only if their corresponding push-back rate is less that the push-back threshold in addition to the corresponding hit rate being less than the hit threshold.
21. The storage circuit of claim 12, wherein when the individual storage tiles are in the power-saving state, the control logic within the individual storage tiles further determines whether or not the individual storage tiles should leave the power-saving state by measuring the activity level at the individual storage tiles and comparing the activity level to an inactivity threshold.
22. The storage circuit of claim 21, wherein the activity level at the individual storage tiles while the individual storage tiles are in the power-saving state is a corresponding push-back rate of the individual storage tiles and wherein the inactivity threshold is a push-back threshold.
23. A method of power managing a spiral cache memory comprising a plurality of storage tiles, the method comprising:
moving values stored within the plurality of storage tiles according to a movement heuristic via an internal network of the spiral cache memory to automatically transfer the values according to the movement heuristic to provide vacant storage locations for other values written to the spiral cache memory from an external device,
for storage tiles within the spiral cache memory that are in a fully active state, measuring a hit rate and a push-back rate at the storage tiles, comparing the push-back rate to a push-back threshold and the hit rate to a hit threshold, wherein the push-back rate is a rate of internal transfer among the storage tiles within the spiral cache memory in a direction toward an external backing store, and readying the storage tiles to enter a power-saving state if the push-back rate is less than the push-back threshold and the hit rate is less than the hit threshold; and
for storage tiles in a power-saving state, measuring a push-back rate at the storage tiles, comparing the push-back rate to a second push-back threshold, and placing the storage tiles in the fully active state if the push-back rate is greater than the second push-back threshold, wherein the values stored in the tiles that are in the fully active state are transferred according to the movement heuristic to be stored in next tiles, and wherein the values transferred according to the movement heuristic bypass the tiles that are in the power-saving state without being stored in the tiles that are in the power-saving state.
24. The method of claim 23, further comprising:
sending power management status requests to the individual storage tiles to query the individual tiles as to whether the individual tiles are ready to enter the power-saving state; and
sending responses from the individual storage tiles indicating whether or not they are ready to enter the power-saving state;
responsive to receiving a response that a corresponding storage tile is ready to enter the power-saving state, sending multiple requests to the corresponding storage tile to push-back dirty values to a push-back interface; and
sending a command to the corresponding storage tile to enter the power-saving state, and wherein the placing the individual storage tiles in the power-saving state is further performed only in response to receiving the command.
25. The method of claim 24, further comprising:
subsequent to the sending of the multiple requests to the corresponding storage tile to push-back dirty values, waiting a predetermined period for the dirty values to enter a push-back queue; and
determining whether the push-back queue has a predetermined number of open entries, and wherein the sending a command is performed only in response to determining that the push-back queue has a predetermined number of open entries after the multiple requests have been sent.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An active plate, comprising:
a substrate;
a first metallisation layer defining gate electrodes and further defining first storage capacitor electrodes extending longitudinally across the substrate;
a second metallisation layer defining source and drain electrodes and second storage capacitor electrodes;
a semiconductor body layer forming thin film transistor bodies between the source and drain electrodes; and
an insulation layer between first and second storage capacitor electrodes,
wherein the drain electrode extends across the width of the gate electrode, and the second storage capacitor electrode overlaps the lateral edges of the first storage capacitor electrode.
2. An active plate according to claim 1 wherein the width of the gate electrode is from 0.8 to 1.2 times the width of the first storage capacitor electrode.
3. An active plate according to claim 1 wherein the semiconductor body extends longitudinally over the gate electrode.
4. An active plate according to claim 1 wherein the second storage capacitor electrode is formed from a plurality of elements having a width within a factor of 2 of the width of the drain electrode.
5. An active plate according to claim 4 wherein the plurality of elements extend laterally across the first storage capacitor electrode.
6. An active plate according to claim 5 wherein the second storage capacitor electrode is formed from a plurality of elements extending laterally across the width of the first capacitor electrode and connected together by at least one longitudinal element.
7. A liquid crystal display comprising an active plate, a passive plate and liquid crystal between the active and passive plates, the active plate comprising a substrate;
a first metallisation layer defining gate electrodes and further defining first storage capacitor electrodes extending longitudinally across the substrate;
a second metallisation layer defining source and drain electrodes and second storage capacitor electrodes;
a semiconductor body layer forming thin film transistor bodies between the source and drain electrodes; and
an insulation layer between first and second storage capacitor electrodes,
wherein the drain electrode extends across the width of the gate electrode, and the second storage capacitor electrode overlaps the lateral edges of the first storage capacitor electrode.
8. A method of manufacture of an active plate, comprising the steps of:
depositing and patterning using a lower definition patterning process a first metallisation layer on a substrate, the first metallisation layer defining gate electrodes and first storage capacitor electrodes extending longitudinally across the substrate;
depositing an insulation layer;
depositing and patterning using a lower definition patterning process a semiconductor body layer forming thin film transistor bodies; and
depositing and patterning using a higher definition process a second metallisation layer defining source and drain electrodes and second storage capacitor electrodes,
wherein the second storage capacitor electrodes overlap the lateral edges of the first storage capacitor electrode.
9. A method according to claim 8 wherein the drain electrode extends across the width of the gate electrode.
10. A method according to claim 8 wherein the higher definition process is photolithography and the lower definition process is printing.