1. A method of repairing a circuit, comprising:
positioning a circuit in a vacuum chamber;
creating a layer of at least one reactive material in proximity with a surface of the circuit;
exciting a portion of the layer of reactive materials to form chemical radicals;
removing a portion of the surface of the circuit to expose at least one defect;
at least one of etching to remove a first defective portion of the circuit, and depositing a material to fill a second defective portion of the circuit; and
depositing at least one material to replace the removed portion of the surface of the circuit.
2. The method of claim 1, wherein the etching to remove the first defective portion of the circuit comprises creating a layer of a second at least one reactive material in proximity with the surface and the exposed defect of the circuit, exciting a portion of the layer of the second reactive materials to form chemical radicals to etch and remove the first defective portion of the circuit.
3. The method of claim 1, wherein the depositing to fill a second defective portion of the circuit comprises creating a layer of a third at least one reactive material in proximity with the surface and the exposed defect of the circuit, exciting a portion of the layer of the third reactive materials to form chemical radicals to deposit a material compatible with the second defective portion of the circuit and fill the second defective portion of the circuit.
4. The method of claim 1, wherein the depositing at least one material to replace the removed portion of the surface of the circuit comprises creating a layer of a fourth at least one reactive material in proximity with the surface and the exposed defect of the circuit, exciting a portion of the layer of the fourth reactive materials to form chemical radicals to deposit at least one material compatible with the removed portion of the circuit, and to fill the removed portion of the circuit.
5. The method of claim 4, wherein at least one of the reactive materials includes at least one material that does not directly interact with the other reactive materials.
6. The method of claim 1, wherein the reactive materials includes a halogen.
7. The method of claim 6, wherein the halogen comprises xenon fluoride.
8. The method of claim 1, wherein exciting a portion of the layer of reactive materials to form chemical radicals comprises an energetic beam including at least one of an electron beam, ion beam, laser beam, microwave beam and X-ray beam.
9. The method of claim 8, wherein an area containing the chemical radicals has a diameter of less than 0.10\u03bc.
10. The method of claim 9, wherein the energetic beam is an electron beam which comprises a portion of a scanning electron microscope disposed to provide an image of the portion of the surface of the circuit.
11. The method of claim 1, wherein the at least one reactive material is changed, as the surface of the circuit is removed to expose the at least one defect, to selectively remove different material layers above the at least one defect.
12. The method of claim 1, wherein removing a portion of the surface creates reaction products analyzed by at least one of residual gas analyzer, mass spectroscopy, optical emission spectroscopy, atomic absorption spectroscopy, infrared spectroscopy, Raman spectroscopy and energy dispersive analysis of X-rays.
13. The method of claim 1, wherein a vacuum pressure of the vacuum chamber is determined by a desired mean free path of the chemical radicals generated by the exciting a portion of the layer of reactive materials to form chemical radicals.
14. The method of claim 13, wherein the at least one reactive material is one of a gas, a liquid and a solid at standard temperature and pressure which sublimes in the vacuum chamber at the determined vacuum pressure.
15. The method of claim 2, wherein the defective portion of the circuit includes a conductive material that one of shorts two signals lines, creates a leakage path, is an unblown fuse link, and is a circuit design error.
16. The method of claim 3, wherein the defective portion of the circuit includes a conductive material that one of open circuits a signal line, open circuits a power line, open circuits a clock line, is a blown fuse link, and is a circuit design error.
17. The method of claim 3, wherein the defective portion of the circuit includes at least one of a void in an insulator layer, an incompletely etched contact forming an open circuit, and an oxidized surface of a conductive material.
18. The method of claim 1, wherein creating a layer of reactive material in proximity with the surface includes at least one of directed gas flow, gaseous diffusion through a showerhead, sublimation of a solid material, bubbling an inert gas through a liquid material, and spraying a liquid.
19. The method of claim 1, wherein the at least one reactive material includes at least one of halogen, a metallo-halide, a metallo-organic, a silane, and oxygen.
20. The method of claim 1, wherein the circuit includes an integrated circuit.
21. A method of repairing a circuit, comprising:
positioning a circuit in a vacuum chamber;
creating a combination of reactive materials in proximity with a surface of the circuit;
exciting a portion of the layer of reactive materials to form chemical radicals;
removing a portion of the surface of the circuit to expose at least one defect;
at least one of etching to remove a defective portion of the circuit, depositing a material to fill a defective portion of the circuit, depositing at least one material to replace the removed portion of the circuit; and
testing the repaired circuit.
22. The method of claim 21, wherein the exciting a portion of the layer of reactive materials to form chemical radicals comprises an energetic beam.
23. The method of claim 22, wherein the vacuum chamber is a portion of a scanning electron microscope disposed to image the circuit, the energetic beam comprises the electron beam of the scanning electron microscope, and the scanning electron microscope provides an image of the circuit to determine the location and status of a defective portion of the circuit.
24. The method of claim 21, wherein each one of the etching to remove a defective portion of the circuit, depositing to fill a defective portion of the circuit and depositing to replace the removed portion of the circuit, comprise at least one separate combination of reactive materials excited to form radicals.
25. The method of claim 21, wherein the defective portion of the circuit includes at least one of:
a conductive material that one of shorts two signals lines, creates a leakage path, is an unblown fuse link, and is a circuit design error;
a conductive material that one of open circuits a signal line, open circuits a power line, open circuits a clock line, is a blown fuse link, and is a circuit design error; and
a void in an insulator layer, an incompletely etched contact forming an open circuit, and an oxidized surface of a conductive material.
26. The method of claim 21, wherein the combination of reactive materials includes at least one of a liquid, a gas, a solid that sublimates in a vacuum, and comprises at least one of a halogen containing material, a metallo-halide, a metallo-organic, a silane, oxygen, and an inert material that does not chemically react with any of the other materials in the combination under the conditions of the vacuum chamber.
27. The method of claim 21, wherein removing a portion of the surface creates chemical reaction products that may be analyzed by at least one of residual gas analyzer, mass spectroscopy, optical emission spectroscopy, atomic absorption spectroscopy, infrared spectroscopy, Raman spectroscopy and energy dispersive analysis of X-rays.
28. The method of claim 27, wherein the circuit is an integrated circuit and the analysis provides an endpoint detector for an etch stop between one layer of the integrated circuit and a second layer of the integrated circuit.
29. A system for repairing integrated circuits, comprising:
a vacuum chamber;
a first gas inlet for creating a layer of a selected chemical combination in proximity with a surface of the sample;
a first energetic beam directed at a selected location on the surface of the integrated circuit with sufficient energy to form chemical radicals from at least one component of the selected chemical combination;
an analysis device for examining material removed from the surface of the sample and determining when a defect location has been exposed;
a second gas inlet for creating a second layer of a second chemical combination in proximity with the surface of the sample; and
a second energetic beam with sufficient energy to form chemical radicals from at least one component of the second chemical combination.
30. The system of claim 29, wherein the first and second energetic beams include an electron beam.
31. The system of claim 30, wherein the electron beam is a portion of a scanning electron microscope.
32. The system of claim 31, wherein the electron microscope is disposed to provide images of the selected area during the formation of chemical radicals.
33. The system of claim 29, wherein the selected chemical combination comprises a halogen containing compound.
34. The system of claim 29, wherein the first and second gas inlets for creating a layer of selected chemical combinations in proximity with the surface of the sample includes a directed gas jet, a gaseous diffusion head, a sublimation device, a bubbler and a liquid spray device.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of neutralizing holes in the tunnel oxide of a floating-gate memory cell, the method comprising:
after applying a positive voltage to a source of the memory cell relative a common voltage while applying a first negative voltage to a control gate of the memory cell relative the common voltage, discharging the positive voltage and disabling any voltage regulation of the first negative voltage; and
allowing the first negative voltage to discharge for a predetermined period.
2. The method of claim 1, further comprising discharging the positive voltage at a rate sufficient to couple a second negative voltage to a floating gate of the memory cell during the predetermined period.
3. The method of claim 2, wherein discharging the positive voltage occurs in less than 1 ms.
4. The method of claim 2, wherein the second negative voltage has a magnitude of at least about 3 volts.
5. The method of claim 1, wherein holes are neutralized during the predetermined period.
6. The method of claim 1, wherein the predetermined period is at least about 2 ms.
7. The method of claim 6, wherein the predetermined period is at least about 10 ms.
8. The method of claim 1, further comprising programming a duration of the predetermined period after manufacture of a memory device containing the memory cell.
9. The method of claim 1, wherein a magnitude of the second negative voltage is effectively increased by using wordline drive transistors with low parasitic drain capacitance compared with a wordline capacitance.
10. The method of claim 9, wherein the low parasitic drain capacitance is on the order of 1-10 fF.
11. The method of claim 1, wherein disabling any voltage regulation of the first negative voltage further comprises disabling any regulation of the first negative voltage by a negative pump used to supply the first negative voltage.
12. The method of claim 1, wherein the positive voltage is between approximately 4V to 6V.
13. The method of claim 1, wherein the first negative voltage is initially between approximately \u22128V to \u221213V.
14. A method of neutralizing holes in the tunnel oxide of a floating-gate memory cell, the method comprising:
after applying a positive voltage to a source of the memory cell relative a common voltage while applying a first negative voltage to a control gate of the memory cell relative the common voltage, discharging the positive voltage and disabling any voltage regulation of the first negative voltage; and
allowing the first negative voltage to discharge for a predetermined period of at least about 2 ms;
wherein discharging the positive voltage occurs at a rate sufficient to couple a second negative voltage to a floating gate of the memory cell during the predetermined period.
15. The method of claim 14, wherein discharging the positive voltage occurs in less than 1 ms.
16. The method of claim 14, wherein the second negative voltage has a magnitude of at least about 3 volts.
17. The method of claim 14, wherein holes are neutralized during the predetermined period.
18. The method of claim 14, wherein the predetermined period is at least about 10 ms.
19. The method of claim 14, further comprising programming a duration of the predetermined period after manufacture of a memory device containing the memory cell.
20. The method of claim 14, wherein a magnitude of the second negative voltage is effectively increased by using wordline drive transistors with low parasitic drain capacitance compared with a wordline capacitance.
21. The method of claim 20, wherein the low parasitic drain capacitance is on the order of 1-10 fF.
22. The method of claim 14, wherein disabling any voltage regulation of the first negative voltage further comprises disabling any regulation of the first negative voltage by a negative pump used to supply the first negative voltage.
23. The method of claim 14, wherein the positive voltage is between approximately 4V to 6V.
24. The method of claim 14, wherein the first negative voltage is initially between approximately \u22128V to \u221213V.