1. A method of operating a NAND flash memory device, comprising:
receiving command and address signals at a first frequency in response to a clock signal having the first frequency;
increasing the frequency of the clock signal from the first frequency to a second frequency; and
receiving a data signal at the second frequency in response to the clock signal.
2. The method of claim 1, wherein the address signal is a starting address signal.
3. The method of claim 1 further comprises receiving the command, address, and data signals in succession.
4. The method of claim 1, wherein receiving the command and address signals comprises receiving the command signal at a command register of the memory device and receiving the address signal at an address register of the memory device.
5. The method of claim 1, wherein receiving data signal comprises receiving the data signal at a cache register or a data register of the memory device.
6. The method of claim 1 further comprises decoding the address signal.
7. The method of claim 1, wherein the address signal comprises column and row addresses.
8. A method of operating a NAND flash memory device, comprising:
receiving a clock signal at first frequency;
receiving command and address signals that are timed by the clock signal at the first frequency so that command and address signals are received at the first frequency;
receiving the clock signal at a second frequency greater than the first frequency; and
receiving a data signal that is timed by the clock signal at the second frequency so that the data signal is received at the second frequency.
9. The method of claim 8 further comprises receiving the command, address, and data signals in succession.
10. The method of claim 8, wherein the command, address, and data signals are received over a common bus.
11. The method of claim 8, wherein the second frequency commences at a rising clock edge of the clock signal that occurs immediately after a rising clock edge of the clock signal at which a last portion of the address signal was received.
12. A method of operating a NAND flash memory device, comprising:
receiving command and address signals at a first frequency; and
receiving a data signal at a second frequency that is greater than the first frequency;
wherein the second frequency commences after a delay time between receiving a last portion of the address signal and receiving a first portion of the data signal.
13. A method of operating a NAND flash memory device, comprising:
receiving command and address signals at a first frequency; and
receiving a data signal at a second frequency that is greater than the first frequency;
wherein the second frequency commences at a rising clock edge of a clock signal that occurs immediately after a rising clock edge of the clock signal at which a last portion of the address signal was received; and
wherein the clock signal has the first frequency while the command and address signals are received at the first frequency, and the clock signal has the second frequency while the data signal is received at the second frequency.
14. A method of operating a NAND flash memory device, comprising:
receiving command and address signals at a first frequency; and
receiving a data signal at a second frequency that is greater than the first frequency;
wherein the command signal and the address signal are respectively received at immediately successive rising clock edges of a first portion of a clock signal;
wherein a first portion of the data signal is received at a rising clock edge of a second portion of the clock signal, the rising clock edge of the second portion of the clock signal at which the first portion of the data signal is received is located immediately after a rising clock edge of the first portion of the clock signal at which a last portion of the address signal is received;
wherein remaining portions of the data signal are received at immediately successive rising clock edges of the second portion of the clock signal; and
wherein the first portion of the clock signal has the first frequency and the second portion of the clock signal has the second frequency.
15. A method of operating a NAND flash memory device, comprising:
receiving command and address signals at a first frequency; and
receiving a data signal at a second frequency that is greater than the first frequency;
wherein the address signal is received at a rising edge of a clock signal immediately following a rising edge of the clock signal at which the command signal was received.
16. A method of operating a NAND flash memory device, comprising:
receiving command and address signals at a first frequency; and
receiving a data signal at a second frequency that is greater than the first frequency;
wherein the address signal comprises first and second addresses; and
wherein a first portion of the second address is received at a rising edge of a clock signal immediately following a rising edge of the clock signal at which a last portion of the first address was received; and
wherein the clock signal has the first frequency while the command and address signals are received at the first frequency, and the clock signal has the second frequency while the data signal is received at the second frequency.
17. An electronic system, comprising:
a processor; and
a memory device coupled to the processor;
wherein the processor is configured to generate a clock signal having a first frequency in response to the processor transmitting control and address signals to the memory device for timing the control and address signals; and
wherein the processor is configured to increase the frequency of the clock signal from the first frequency to a second frequency in response to the processor transmitting a data signal to the memory device.
18. The electronic system of claim 17, wherein the command, address, and data signals are transmitted in succession.
19. An electronic system, comprising:
a processor;
a NAND flash memory device; and
an inputoutput bus coupled between the processor and the memory device;
wherein the processor is adapted to perform a method, comprising:
transmitting command and address signals at a first frequency to the memory device over the inputoutput bus; and
transmitting a data signal at a second frequency, greater than the first frequency, to the memory device over the inputoutput bus;
wherein the second frequency commences after a delay time between transmitting a last portion of the address signal and transmitting a first portion of the data signal.
20. An electronic system, comprising:
a processor;
a NAND flash memory device; and
an inputoutput bus coupled between the processor and the memory device;
wherein the processor is adapted to perform a method, comprising:
transmitting command and address signals at a first frequency to the memory device over the inputoutput bus; and
transmitting a data signal at a second frequency, greater than the first frequency, to the memory device over the inputoutput bus;
wherein the second frequency commences at a rising clock edge of a clock signal, generated by the processor, that occurs immediately after a rising clock edge of the clock signal at which a last portion of the address signal was transmitted; and
wherein the clock signal has the first frequency while the command and address signals are received at the first frequency, and the clock signal has the second frequency while the data signal is received at the second frequency.
21. An electronic system, comprising:
a processor;
a NAND flash memory device; and
an inputoutput bus coupled between the processor and the memory device;
wherein the processor is adapted to perform a method, comprising:
transmitting command and address signals at a first frequency to the memory device over the inputoutput bus; and
transmitting a data signal at a second frequency, greater than the first frequency, to the memory device over the inputoutput bus;
wherein the address signal is received at a rising edge of a clock signal immediately following a rising edge of the clock signal at which the command signal was received.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1.-7. (canceled)
8. An aircraft wing, comprising:
a wing box formed from a first material;
a leading edge structure formed from a second material and attached to the wing box, the leading edge structure being detachable from the wing box and replaceable; and
a cooling channel extending through the leading edge structure along a direction defined by a span of the leading edge, the cooling channel comprising at least one fluid conduit for communicating a fluid through the leading edge structure for reducing a temperature thereof.
9. An aircraft wing according to claim 8, wherein the second material is selected from the group consisting of refractory metals, refractory alloys, and ceramics.
10. An aircraft wing according to claim 8, wherein the leading edge structure comprises integrally formed stiffeners formed from the second material.
11. An aircraft wing according to claim 8, wherein a leading edge structure has a replaceable tip that is assembled to the leading edge structure with an assembly technique comprising a tolerance fit keyway joint, and the cooling channel extends through the replaceable tip.
12. An aircraft wing according to claim 8, wherein the leading edge structure has a variable geometry extending in a direction defined by a span of the aircraft wing.
13. A method of forming a wing of an aircraft, comprising:
(a) designing a wing as a digital model having a wing box and a leading edge structure;
(b) fabricating the wing box without the leading edge structure from the digital model using a first material; and
(c) directly depositing the leading edge structure directly from the digital model using a second material to directly form the leading edge structure on the wing box at a leading edge spar thereof; and
(d) assembling the leading edge structure to the wing box at a leading edge spar.
14. A method according to claim 13, wherein the second material is selected from the group consisting of refractory metals, refractory alloys, and ceramics.
15. A method according to claim 13, further comprising the steps of fabricating a replaceable tip separately from the leading edge structure, and then mechanically assembling the replaceable tip to the leading edge structure.
16. A method according to claim 13, further comprising forming at least one cooling channel in the leading edge structure for circulating a fluid therethrough for cooling the leading edge structure.
17. A method according to claim 13, further comprising forming stiffening elements in the leading edge structure.
18. A method according to claim 13, further comprising forming the leading edge structure with a variable geometry along a span of the wing.
19. A method of forming a wing of an aircraft, comprising:
(a) designing a wing as a digital model having a wing box and a leading edge structure;
(b) fabricating the wing box without the leading edge structure from the digital model using a first material;
(c) directly depositing the leading edge structure directly from the digital model using a second material to directly form the leading edge structure on the wing box at a leading edge spar thereof; and
(d) forming at least one cooling channel in the leading edge structure for circulating a fluid therethrough for cooling the leading edge structure.
20. A method according to claim 19, wherein the second material is selected from the group consisting of refractory metals, refractory alloys, and ceramics.
21. A method according to claim 19, further comprising the steps of fabricating a replaceable tip separately from the leading edge structure, and then mechanically assembling the replaceable tip to the leading edge structure.
22. A method according to claim 19, further comprising forming stiffening elements in the leading edge structure.