1. A manufacturing method for a semiconductor device comprising the steps of:
(a) preparing a lead frame including a die pad that contains a chip mounting surface, a plurality of suspension leads that support the die pad, a plurality of first leads that are mounted at the periphery of the die pad, a plurality of second leads whose lengths are shorter than the respective first leads, and a common lead that is mounted between the die pad and the second leads as seen from a plan view;
(b) mounting a semiconductor chip formed with a plurality of electrode pads over the main surface over the chip mounting surface of the die pad;
(c) coupling electrically by way of a plurality of wires, each of the electrode pads of the semiconductor chip, the common lead, and the first leads and the second leads;
(d) sealing the common lead, the semiconductor chip, and the wires with resin so that a portion of each of the first and second leads and the common lead are exposed from the sealing body; and
(e) cutting a plurality of outer leads that are exposed from the sealing body from the lead frame;
wherein, in the step (c):
a first wire among the wires electrically couples the electrode pad and the first lead,
a second wire among the wires passes over the common lead and electrically couples the electrode pad and any lead of the second leads,
a third wire among the wires passes over the common lead and also electrically couples the electrode pad and any of the another second leads at a loop height higher than the second wire, and
the second wire is mounted closer than the third wire in the common lead region corresponding to the common lead, relative to the standard suspension lead at the position matching the gate for supplying resin during the resin sealing among the suspension leads.
2. The manufacturing method for a semiconductor device according to claim 1,
wherein, in the step (c):
a fourth wire having a loop height lower than the second wire is mounted near the second wire on the standard suspension lead side of the second wire in the common lead region in order to electrically couple to a common lead.
3. The manufacturing method for a semiconductor device according to claim 2,
wherein, in the step (c):
the electrode pad for the semiconductor chip where no wire is coupled is mounted on the standard suspension lead side of the fourth wire in the common lead region.
4. The manufacturing method for a semiconductor device according to claim 3,
wherein, in the step (c):
the second wire is electrically coupled to the second lead at a position on the end nearest the standard suspension lead in the common lead region.
5. The manufacturing method for a semiconductor device according to claim 1,
wherein, in the step (c):
a fourth wire is mounted adjacent to the second wire in the common lead region, and also nearer the standard suspension lead than the second wire by setting a loop height of the fourth wire lower than the second wire, and the fourth wire is electrically coupled to the common lead.
6. The manufacturing method for a semiconductor device according to claim 2,
wherein, in the step (c):
a fifth wire having a loop height lower than the fourth wire is electrically coupled to the die pad.
7. The manufacturing method for a semiconductor device according to claim 1,
wherein the wire includes material whose main constituent is copper.
8. A semiconductor device comprising:
a die pad that includes a chip mounting surface;
a plurality of first leads that are mounted at the periphery of the die pad;
a plurality of second leads whose length is shorter than the respective first leads;
a common lead that is mounted between the die pad and the second leads as seen from a plan view;
a semiconductor chip that is mounted over the chip mounting surface of the die pad, and where a plurality of electrode pads are formed over the main surface of the chip;
a plurality of first wires that electrically couple the electrode pads of the semiconductor chip and the first leads;
a plurality of second wires or third wires that electrically couple the electrode pads of the semiconductor chip and the second leads;
a sealing body that seals a portion of the die pad, the common lead, the semiconductor chip, and the first, second, and third wires; and
a plurality of outer leads that are exposed from the sealing body,
wherein the second and the third wire are respectively formed to pass over the common lead,
wherein the loop height of the second wire is lower than the loop height of the third wire, and
wherein the heights of the common lead and the tips at the die pad side of each of the second leads, are the same.
9. The semiconductor device according to claim 8,
wherein the first, the second, and the third wire include a material whose main constituent is copper.
10. The semiconductor device according to claim 9,
wherein the rear side of the die pad is exposed at the rear side of the sealing body.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A plasma display panel, comprising:
a scan electrode and a sustain electrode parallel with each other on a front substrate;
a data electrode on a back substrate positioned orthogonally to the scan electrode and the sustain electrode, the back substrate facing the front substrate with a discharge space therebetween;
and
a first discharge space and a second discharge space between the front substrate and the back substrate partitioned apart by a barrier rib, wherein
a main discharge cell for performing a discharge with the scan electrode, the sustain electrode and the data electrode is in the first discharge space, a dielectric layer is on the back substrate in the second discharge space covering the data electrode, a priming electrode, independent of the data electrode, is on the dielectric layer so that the priming electrode is parallel to the scan electrode and the sustain electrode, and a priming discharge cell for performing a discharge with the scan electrode and the priming electrode is in the second discharge space, with different voltage signals applied to the priming electrode and the data electrode.
2. The plasma display panel according to claim 1, wherein
the barrier rib is a longitudinal rib part extending in the direction orthogonal to the scan electrode and the sustain electrode, and a lateral rib part forming a gap part of continuous groove shape parallel with the scan electrode and the sustain electrode, and
the gap part forms the second discharge space.
3. A method for manufacturing a plasma display panel, comprising:
forming a main discharge cell in a first discharge space, the main discharge cell comprising:
a scan electrode and a sustain electrode parallel with each other on a front substrate;
a data electrode on a back substrate positioned orthogonally to the scan electrode and the sustain electrode, the back substrate facing the front substrate with a discharge space therebetween; and
the first discharge space and a second discharge space are between the front substrate and the back substrate partitioned apart by a barrier rib, and the main discharge cell for performing a discharge with the scan electrode, the sustain electrode and the data electrode;
forming a dielectric layer on the back substrate in the second discharge space covering the data electrode;
forming a priming electrode, independent of the data electrode, on the dielectric layer parallel to the scan electrode and the sustain electrode, with different voltage signals applied to the priming electrode and the data electrode; and
forming a priming discharge cell in the second discharge space, the priming discharge cell performing a discharge with the priming electrode and the scan electrode,
forming the second discharge space comprising:
forming the dielectric layer continuously in a longitudinal direction orthogonal at least to the data electrode; and
forming the priming electrode continuous on the dielectric layer.
4. The method for manufacturing the plasma display panel according to claim 3, wherein
forming the dielectric layer comprises filling dielectric paste into the second discharge space by discharging the dielectric paste at least through a nozzle.
5. The method for manufacturing the plasma display panel according to claim 4 further comprising continuously filling the dielectric layer after the barrier rib is patterned on the back substrate.
6. The method for manufacturing the plasma display panel according to claim 5, wherein
the barrier rib and the dielectric layer concurrently undergo firing and solidification.
7. The method for manufacturing the plasma display panel according to claim 3, wherein
forming the priming electrode comprises filling electrode material paste into the second discharge space by discharging the electrode material paste at least through a nozzle.