1. A system comprising:
a memory;
a processor; and
an integrated circuit (IC) chip coupled to the memory and to the processor, the IC chip comprising:
a plurality of input-output (IO) cells;
a controller to exchange signals between the memory and the processor through the plurality of IO cells; and
a protocol sequence generator to generate test signals to test characteristics of the plurality of IO cells, wherein the protocol sequence generator generates the test signals based on at least one control signal.
2. The system as claimed in claim 1, wherein each of the plurality of IO cells is a dual data rate (DDR) IO cell.
3. The system as claimed in claim 1, wherein the protocol sequence generator generates the test signals based, at least in part, on an external clock signal.
4. The system as claimed in claim 1, wherein at least one of the test signals is selected from a group of a DDR clock signal, a data strobe signal, and a pre-defined number of bits of data signal.
5. The system as claimed in claim 1, wherein the protocol sequence generator simulates the test signals corresponding to a write cycle in the memory.
6. The system as claimed in claim 1, wherein the controller, in a normal mode of operation, generates controller data signals for the plurality of IO cells.
7. The system as claimed in claim 6 further comprising a switching unit to provide the controller data signals to the plurality of IO cells during the normal mode of operation and to provide the test signals to the plurality of IO cells during a test mode of operation.
8. An integrated circuit (IC) chip comprising:
a plurality of dual data rate (DDR) input-output (IO) cells; and
a DDR protocol sequence generator (DPSG) coupled to the DDR IO cells, the DPSG comprising,
a control unit to receive at least one control signal to generate at least one synchronized control signal, wherein the at least one synchronized control signal is synchronized with an external clock signal; and
a sequencing unit to receive the external clock signal and the at least one synchronized control signal to generate test signals.
9. The IC chip as claimed in claim 8, wherein the DPSG further comprises a data unit to generate write data signals for the test signals.
10. The IC chip as claimed in claim 9, wherein the data unit selects the write data signals, based on a data select signal, from internal data signals and external data signals.
11. The IC chip as claimed in claim 8, wherein the DPSG further comprises a clock generator to receive the external clock signal to generate a DDR clock signal having a frequency that is half the frequency of the external clock signal.
12. The IC chip as claimed in claim 8, wherein the IC chip further comprises a memory.
13. The IC chip as claimed in claim 8, wherein the control unit further comprises a counting unit to initiate a counter based on receiving the at least one synchronized control signal, wherein the counter generates counter signal bits to sequence the test signals.
14. The IC chip as claimed in claim 8, wherein the sequencing unit generates test signals comprising a DDR clock signal, a data strobe signal, and at least one bit of data signal.
15. A sequencing unit for sequencing test signals, the sequencing unit comprising:
a data sampler to sample write data signals and internal data enable signals at an edge of an external clock signal to generate at least one bit of a data signal and corresponding data enable signals; and
a data strobe sampler to sample an internal data strobe signal and an internal data strobe enable signal at an opposite edge of the external clock signal to generate a data strobe signal and corresponding data strobe enable signal.
16. The sequencing unit as claimed in claim 15, wherein the sequencing unit comprises a data strobe sequencing unit to determine, based on a data debug signal, a pre-defined number of the at least one bit of the data signal.
17. A method comprising:
receiving at least one control signal to generate, based on an external clock signal, a synchronized control signal; and
generating test signals to test characteristics of a plurality of input-output (IO) cells in an integrated circuit (IC) chip based on the synchronized control signal and the external clock signal.
18. The method as claimed in claim 17 further comprising generating the test signals corresponding to a write cycle in DDR SDRAM memory.
19. The method as claimed in claim 17 further comprising generating the test signals having a DDR clock signal, a data strobe signal, and a write enable signal.
20. The method as claimed in claim 19 further comprising edge aligning the DDR clock signal with the data strobe signal.
21. The method as claimed in claim 19 further comprising generating the test signals having at least one bit of data signal.
22. The method as claimed in claim 21 further comprising center aligning the data strobe signal with the at least one bit of data signal.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A system comprising:
a deposition system configured to deposit a solder outwardly from at least one substrate of a plurality of substrates; and
a plasmabonding system comprising:
a plasma system configured to plasma clean the at least one substrate; and
a bonding system configured to bond the plurality of substrates, the plasmabonding system configured to at least reduce reoxidation of the solder.
2. The system of claim 1, the plasmabonding system comprising:
a chamber in which the at least one substrate is plasma cleaned and the plurality of substrates are bonded.
3. The system of claim 1, the plasmabonding system comprising:
a plasma chamber in which the at least one substrate is plasma cleaned; and
a bonding chamber in which the plurality of substrates are bonded, the bonding chamber coupled to the plasma chamber.
4. The system of claim 1, the plasmabonding system comprising:
a plasma chamber in which the at least one substrate is plasma cleaned;
a bonding chamber in which the plurality of substrates are bonded; and
a load-lock module configured to couple the plasma chamber and the bonding chamber under a substantial vacuum.
5. The system of claim 1, the plasmabonding system comprising:
a vacuum chamber within which there is a substantial vacuum;
a plasma chamber disposed within the vacuum chamber and in which the at least one substrate is plasma cleaned; and
a bonding chamber disposed within the vacuum chamber and in which the plurality of substrates are bonded.
6. The system of claim 1, the plasmabonding system comprising:
a nitrogen chamber configured to use nitrogen gas to push oxygen gas outside of the nitrogen chamber;
a plasma chamber disposed within the nitrogen chamber and in which the at least one substrate is plasma cleaned; and
a bonding chamber disposed within the nitrogen chamber and in which the plurality of substrates are bonded.
7. The system of claim 1, the plasmabonding system configured to:
a vacuum chamber within which there is a substantial vacuum;
a plasma chamber disposed within the vacuum chamber and in which the at least one substrate is plasma cleaned;
a bonding chamber disposed within the vacuum chamber and in which the plurality of substrates are bonded; and
a module configured to couple the plasma chamber and the bonding chamber.
8. A method comprising:
depositing a solder outwardly from at least one substrate of a plurality of substrates;
plasma cleaning the at least one substrate;
at least reducing reoxidation of the solder; and
bonding the plurality of substrates.
9. The method of claim 8, the at least reducing reoxidation of the solder comprising:
plasma cleaning the at least one substrate in a chamber; and
bonding the plurality of substrates in the chamber.
10. The method of claim 8, the at least reducing reoxidation of the solder comprising:
plasma cleaning the at least one substrate in a plasma chamber; and
bonding the plurality of substrates in a bonding chamber coupled to the plasma chamber.
11. The method of claim 8, the at least reducing reoxidation of the solder comprising:
plasma cleaning the at least one substrate in a plasma chamber;
transporting the at least one substrate to a bonding chamber through a load-lock module coupling the plasma chamber and the bonding chamber under a substantial vacuum; and
bonding the plurality of substrates in the bonding chamber.
12. The method of claim 8, the at least reducing reoxidation of the solder comprising:
plasma cleaning the at least one substrate in a plasma chamber disposed within a vacuum chamber within which there is a substantial vacuum; and
bonding the plurality of substrates in a bonding chamber disposed within the vacuum chamber.
13. The method of claim 8, the at least reducing reoxidation of the solder comprising:
plasma cleaning the at least one substrate in a plasma chamber disposed within a nitrogen chamber configured to use nitrogen gas to push oxygen gas outside of the nitrogen chamber; and
bonding the plurality of substrates in a bonding chamber disposed within the nitrogen chamber.
14. A method comprising:
depositing solder outwardly from a first substrate;
removing metal oxide from the first substrate; and
depositing a capping layer outwardly from the first substrate to at least reduce reoxidation of the solder.
15. The method of claim 7, further comprising:
bonding the first substrate and a second substrate.
16. The method of claim 7, further comprising:
allowing the first substrate to be exposed to atmosphere prior to bonding the first substrate and a second substrate.
17. The method of claim 7, the capping layer comprising gold.
18. A system comprising:
a deposition system configured to deposit a solder outwardly from a first substrate; and
a plasmabonding system configured to:
remove metal oxide from the first substrate; and
deposit a capping layer outwardly from the first substrate to at least reduce reoxidation of the solder.
19. The system of claim 18, the plasmabonding system configured to:
bond the first substrate and a second substrate.
20. The system of claim 18, the plasmabonding system configured to:
allow the first substrate to be exposed to atmosphere prior to bonding the first substrate and a second substrate.