1. A method for retrieving performance data from storage area network (SAN) devices, each SAN device corresponding to a device plug-in (DPI), the method comprising:
determining a minimum polling interval for polling a SAN device;
determining a maximum polling interval for polling the SAN device; and
using the DPI to retrieve the performance data from the corresponding SAN device by polling the SAN device.
2. The method of claim 1, further comprising polling each SAN device at an interval between the minimum polling interval and the maximum polling interval.
3. The method of claim 1, wherein the using the DPI step further comprises using a performance interface to retrieve performance data by polling the corresponding SAN device.
4. The method of claim 1, further comprising instructing the DPI to communicate directly with the SAN device using simple network management protocol.
5. The method of claim 1, further comprising instructing the DPI to communicate with a host machine to retrieve performance data from a storage array.
6. The method of claim 1, wherein the using the DPI step further comprises communicating with an abstract data source that has a one-to-one relationship with the SAN device, wherein the abstract data source receives from and transmits data to the corresponding DPI.
7. The method of claim 6, wherein the abstract data sources are Java code.
8. The method of claim 1, further comprising providing the DPI with an address of the corresponding SAN device.
9. A system for retrieving performance data from storage area network (SAN) devices, comprising:
a plurality of device plug-ins (DPIs), wherein each DPI corresponds to a SAN device and comprises:
a minimum polling indicator determining a minimum polling interval for polling the corresponding SAN device; and
a maximum polling indicator determining a maximum polling interval for polling the corresponding SAN device; and
a performance application that uses the plurality of DPIs to retrieve the performance data from the corresponding SAN devices by polling the SAN devices.
10. The system of claim 9, wherein each DPI further comprises a performance interface that enables each SAN device to be polled.
11. The system of claim 9, wherein each DPI communicates directly with the corresponding SAN device using simple network management protocol.
12. The system of claim 9, wherein each DPI communicates with a host machine to retrieve performance data from a storage array.
13. The system of claim 9, wherein each DPI further comprises an address indicator that provides the DPI with an address of the corresponding SAN device.
14. The system of claim 9, wherein each DPI further comprises a function indicator instructing the DPI to retrieve performance data from the corresponding SAN device.
15. The system of claim 9, further comprising a plurality of abstract data sources, wherein each abstract data source corresponds to a SAN device, and receives from and transmits data to the corresponding DPI.
16. The system of claim 9, wherein the performance application polls the SAN devices at an interval between the minimum polling interval and the maximum polling interval.
17. The system of claim 9, wherein each DPI reads log files maintained by the corresponding SAN device to retrieve the performance data.
18. The system of claim 9, wherein each DPI navigates a structure of internal counters maintained by the corresponding SAN device.
19. The system of claim 9, wherein each DPI implements specific application programming interface (API) calls into management software for the corresponding SAN device.
20. A computer readable medium providing instructions for retrieving performance data from storage area network (SAN) devices, each SAN device corresponding to a device plug-in (DPI), the instructions comprising:
determining a minimum polling interval for polling a SAN device;
determining a maximum polling interval for polling the SAN device; and
using the DPI to retrieve the performance data from the corresponding SAN device by polling the SAN device.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A digital processing device, comprising:
n processors, n being a natural number and the same as or larger than 2, wherein the n processors include a main processor and n-1 application processors coupled to the main processor through each separate bus and perform an operation according to a control signal inputted through a control bus; and
a shared memory including a storage area having at least one common section coupled to the main processor and the n-1 application processors through each separate bus, and outputting access information related to whether at least one of the n processors is accessing the at least one common section, n access ports corresponding to the n processors, respectively, and an internal controller configured to generate and output to the corresponding processor the access information related to whether the at least one of the n processors is accessing or attempts to access the at least one common section,
wherein the storage area further comprises c dedicated sections, respectively, allotted to be permitted to be accessed by a predetermined processor of the n processors, c being a natural number,
wherein the at least one common section is an area of the storage area that is accessible individually by k processors, k being a natural number and 2=k=n, during a non-overlapping period of time, and is an area of the storage area for writing or reading operation result values to be communicated between the n processors,
wherein the main processor performs a processing operation by accessing a first dedicated section of the c dedicated sections until an operation result value is computed per a processing unit for all operation result values, and writes each computed operation result value in the at least one common section once each operation result value is computed, whereby, during access of the at least one common section by the main processor, the internal controller provides to the n-1 application processors through one interrupt pin, the access information indicating access of the at least one common section by the main processor while the main processor is accessing the at least one common section, and
wherein subsequently the n-1 application processors access the at least one common section, read the written operation result values of the at least one common section, maintain the access to the at least one common section until all operation result values written in the at least one common section are read, write the read operation result values in a second dedicated section of the c dedicated sections, and perform an operation corresponding to the processing command received from the main processor, whereby, during access of the at least one common section by the n-1 processors, the internal controller provides to the main processor through another interrupt pin, the access information indicating the access of the at least one common section by the n-1 application processors while the n-1 application processors are accessing the at least one common section.
2. The device of claim 1, wherein at least one of basic data for computing the operation result value per processing unit and an operation intermediate value is written in the first dedicated section.
3. The device of claim 1, wherein the at least one common section is a plurality of common sections, and the number of interrupt pins is identical to that of the plurality of common sections.
4. The device of claim 1, wherein the access information is outputted as a first type signal if another of the n processors is accessing or attempts to access the at least one common section and is outputted as a second type signal if the another of the n processors does not access the at least one common section.
5. The device of claim 4, wherein, while the first type signal is inputted, the another processor which has transmitted an access request to the shared memory re-transmit the access request to the shared memory after the access information, renewed into the second type signal, is inputted.
6. The device of claim 1, wherein each processor inputs an access request including at least one of address information and the control signal into the shared memory in order to access the shared memory.
7. The device of claim 6, wherein the control signal comprises an address signal directed to the at least one common section, and a chip select signal of the shared memory.
8. The device of claim 7, wherein the address signal comprises a bank address pointing to the at least one common section.
9. The device of claim 6, wherein the control signal comprises a mode register set (MRS) signal and a chip select signal of the shared memory.
10. The device of claim 1, wherein the shared memory generates and outputs the access status information by referring to a value written in a predetermined section by one of the n processors, in order that the one of the n processors accesses the at least one common section.
11. A memory device shared by a plurality of processors, the memory device comprising:
n access ports coupled to corresponding n processors, n being a natural number and the same as or larger than 2;
a storage area having at least one common section which is allotted to be accessible individually by k processors, k being a natural number and 2=k=n, during a non-overlapping period of time, and a plurality of dedicated sections respectively corresponding to the n processors that are allotted to be permitted to be accessed by the n processors; and
an internal controller configured to generate and output to the corresponding n processors access information related to whether one processor of the n processors is accessing or attempts to access the at least one common section,
wherein the at least one common section is an area for writing or reading operation result values to be communicated between the n processors,
wherein the one processor performs a processing operation by accessing a first dedicated section of the plurality of dedicated sections until an operation result value is computed per a processing unit for all operating result values, and writes each computed operation result value in the at least one common section once each operation result value is computed, whereby, during access of the at least one common section by the one processor, the internal controller provides to n-1 processors through one interrupt pin, the access information indicating access of the at least one common section by the one processor while the one processor is accessing the at least one common section, and
wherein subsequently the n-1 processors access the at least one common section, read the written operation result values of the at least one common section, maintain the access to the at least one common section until all operation result values written in the at least one common section are read, write the read operation result values in a second dedicated section of the plurality of dedicated sections, and perform an operation corresponding to the processing command received from the one processor, whereby, during access of the at least one common section by the n-1 processors, the internal controller provides to the one processor through another interrupt pin, the access information indicating the access of the at least one common section by the n-1 processors while the n-1 processors are accessing the at least one common section.
12. The device of claim 11, wherein at least one of basic data for computing the operation result value per processing unit and an operation intermediate value is written in the first dedicated section.
13. The device of claim 11, wherein the number of interrupt pins is identical to that of the plurality of common sections.