1. A parallax barrier for a three-dimensional (3D) image display, comprising:
a first substrate;
a second substrate opposite to the first substrate;
a first gap control electrode disposed on the first substrate;
a first passivation layer disposed on the first gap control electrode;
a liquid crystal control electrode disposed on the first passivation layer;
an opposing electrode disposed on the second substrate; and
a liquid crystal layer interposed between the first substrate and the second substrate,
wherein the liquid crystal control electrode includes a plurality of unit liquid crystal control electrodes,
wherein two neighboring unit liquid crystal control electrodes are spaced apart with a gap, and
wherein the first gap control electrode overlaps the gap between the unit liquid crystal control electrodes.
2. The parallax barrier for the 3D image display of claim 1, wherein
at least a portion of the first gap control electrode and at least a portion of the opposing electrode are applied with different voltages such that a block portion is formed in the liquid crystal layer corresponding to the gap between the unit liquid crystal control electrodes.
3. The parallax barrier for the 3D image display of claim 2, wherein
the first gap control electrode includes a plurality of unit gap control electrodes,
two neighboring unit gap control electrodes are spaced apart from each other, and
each of the unit gap control electrodes overlaps the gap between two corresponding unit liquid crystal control electrodes.
4. The parallax barrier for the 3D image display of claim 3, wherein
a voltage applied to a portion of the unit gap control electrodes is substantially the same as a voltage applied to the opposing electrode.
5. The parallax barrier for the 3D image display of claim 4, wherein
the opposing electrode includes a plurality of unit opposing electrodes,
two neighboring unit opposing electrodes are spaced apart from each other with a gap, and
each of the unit opposing electrodes overlaps both of two corresponding unit liquid crystal control electrodes.
6. The parallax barrier for the 3D image display of claim 5, further comprising:
a second gap control electrode disposed between the second substrate and the opposing electrode.
7. The parallax barrier for the 3D image display of claim 6, wherein
at least a portion of second gap control electrode and at least a portion of the unit liquid crystal control electrodes are applied with different voltages such that the block portion is formed in the liquid crystal layer corresponding to the gap between the unit opposing electrodes.
8. The parallax barrier for the 3D image display of claim 2, wherein
two neighboring unit liquid crystal control electrodes are applied with different voltages such that the liquid crystal layer corresponding to one of the two neighboring unit liquid crystal control electrodes forms the block portion or an opening portion.
9. The parallax barrier for the 3D image display of claim 2, wherein
at least two neighboring unit liquid crystal control electrodes are applied with a same voltage such that the liquid crystal layer corresponding to the at least two neighboring unit liquid crystal control electrodes forms the block portion or an opening portion.
10. The parallax barrier for the 3D image display of claim 9, further comprising:
a sensing unit which senses a position of an observer,
wherein a position of the block portion or a position of the opening portion corresponding to the unit liquid crystal control electrodes is changed based on the position of the observer sensed by the sensing unit.
11. The parallax barrier for the 3D image display of claim 10, wherein
the first gap control electrode includes a plurality of unit gap control electrodes,
two neighboring unit gap control electrodes are spaced apart from each other, and
each of the unit gap control electrodes overlaps the gap between two corresponding unit liquid crystal control electrodes.
12. The parallax barrier for the 3D image display of claim 11, wherein
a voltage applied to a portion of the unit gap control electrodes is substantially the same as a voltage applied to the opposing electrode.
13. The parallax barrier for the 3D image display of claim 10, wherein
the opposing electrode includes a plurality of unit opposing electrodes,
two neighboring unit opposing electrodes are spaced apart from each other with a gap, and
each of the opposing electrodes overlaps both of two corresponding neighboring unit liquid crystal control electrodes.
14. The parallax barrier for the 3D image display of claim 13, further comprising:
a second gap control electrode disposed between the second substrate and the opposing electrode.
15. The parallax barrier for the 3D image display of claim 14, wherein
at least a portion of the second gap control electrode and at least portion of the unit liquid crystal control electrodes are applied with different voltages such that the block portion is formed in the liquid crystal layer corresponding to the gap between the unit opposing electrodes.
16. A display device comprising:
a parallax barrier; and
a display panel,
wherein the parallax barrier comprises:
a first substrate;
a second substrate opposite to the first substrate;
a first gap control electrode disposed on the first substrate;
a first passivation layer disposed on the first the gap control electrode;
a liquid crystal control electrode disposed on the first passivation layer;
an opposing electrode disposed on the second substrate; and
a liquid crystal layer interposed between the first substrate and the second substrate,
wherein the liquid crystal control electrode includes a plurality of unit liquid crystal control electrodes,
wherein two neighboring unit liquid crystal control electrodes are spaced apart with a gap, and
wherein the first gap control electrode overlaps the gap between the unit liquid crystal control electrodes.
17. The display device of claim 16, wherein
at least a portion of first gap control electrodes and at least a portion of opposing electrodes are applied with different voltages to form a block portion in the liquid crystal layer corresponding to the gap between the unit liquid crystal control electrodes.
18. The display device of claim 17, wherein
the first gap control electrode includes a plurality of unit gap control electrodes,
two neighboring unit gap control electrodes are spaced apart from each other, and
each of the plurality of unit gap control electrodes overlaps the gap between two corresponding unit liquid crystal control electrodes.
19. The display device of claim 18, wherein
a voltage applied to a portion of the unit gap control electrodes is substantially the same as a voltage applied to the opposing electrode.
20. The display device of claim 19, wherein
the opposing electrode includes a plurality of unit opposing electrodes,
two neighboring unit opposing electrodes are spaced apart from each other, and
each of the unit opposing electrodes overlaps both of two corresponding unit liquid crystal control electrodes.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A package comprising:
a substrate configured to support a flip chip die, the flip chip die including a first surface mounted on the substrate and a second surface; and
a thermal collection layer formed on the second surface of the flip chip die, the thermal collection layer configured to dissipate heat generated by the flip chip die.
2. The package of claim 1 further comprising a plurality of bump connections interposed between the substrate and the first surface of the flip chip die.
3. The package of claim 2 wherein the plurality of bump connections include copper.
4. The package of claim 1 wherein the second surface of the flip chip die is opposite the first surface of the flip chip die.
5. The package of claim 1 further comprising a second die interposed between the flip chip die and the substrate.
6. The package of claim 1 further comprising a mold configured to protect the flip chip die and enclose a plurality of exposed surfaces of the flip chip die.
7. The package of claim 1 wherein the thermal collection layer includes copper.
8. A multi-chip package comprising:
a substrate configured to support a plurality of flip chip dies, each flip chip die from the plurality of flip chip dies including a first surface mounted on the substrate and a second surface; and
a thermal collection layer formed on the second surface of each flip chip die from the plurality of flip chip dies, the thermal collection layer configured to dissipate heat generated by the plurality of flip chip dies.
9. The package of claim 8 further comprising a plurality of bump connections interposed between the substrate and the first surface of each flip chip die from the plurality of flip chip dies.
10. The package of claim 9 wherein the plurality of bump connections include copper.
11. The package of claim 8 further comprising a mold configured to protect the package and enclose a plurality of exposed surfaces of the plurality of flip chip dies.
12. The package of claim 8 wherein the thermal collection layer includes copper.
13. The package of claim 8 wherein the plurality of flip chip dies comprises a power amplifier die, a controller die, and a switch die.
14. A method of manufacturing a package including a flip chip die including a plurality of surfaces, the method comprising:
mounting a first surface of the plurality of surfaces of the flip chip die on a substrate;
enclosing exposed surfaces of the plurality of surfaces of the flip chip die with a mold;
removing a portion of the mold to expose a second surface of the plurality of surfaces of the flip chip die, the second surface of the plurality of surfaces of the flip chip die opposite the first surface of the plurality of surfaces of the flip chip die; and
forming a thermal collection layer on the second surface of the plurality of surfaces of the flip chip die, the thermal collection layer configured to dissipate heat generated by the flip chip die.
15. The method of claim 14 further comprising interposing a plurality of bump connections between the substrate and the first surface of the plurality of surfaces of the flip chip die.
16. The method of claim 15 wherein the plurality of bump connections include copper.
17. The method of claim 15 wherein the thermal collection layer includes copper.
18. The method of claim 15 further comprising:
mounting on a substrate a first surface of a plurality of surfaces of a second flip chip die;
enclosing exposed surfaces of the plurality of surfaces of the second flip chip die with the mold;
removing a portion of the mold to expose a second surface of the plurality of surfaces of the second flip chip die, the second surface of the plurality of surfaces of the second flip chip die opposite the first surface of the plurality of surfaces of the second flip chip die; and
forming a thermal collection layer on the second surface of the plurality of surfaces of the second flip chip die, the thermal collection layer further configured to dissipate heat generated by the second flip chip die.
19. A wireless device comprising:
an antenna configured to transmit and receive signals;
a battery configured to power the wireless device; and
a circuit board including a flip chip package having a flip chip die, a substrate mounted on the circuit board and configured to support the flip chip die, and a thermal collection layer configured to dissipate heat generated by the flip chip die.
20. The device of claim 19 wherein the flip chip die includes a first surface mounted on the substrate and a second surface on which the thermal collection layer is formed.
21. The device of claim 20 wherein the flip chip package includes a second flip chip die having a first surface mounted on the substrate and second surface on which the thermal collection layer is formed.