1-13. (canceled)
14: A resonator comprising:
a substrate;
at least two oscillating masses;
means for making the masses oscillate using electrical forces, suspension beams for suspending the masses from the substrate, and coupling beams that link the masses together, wherein the suspension beams are all connected to the masses through the coupling beams, with the suspension beams and the coupling beams forming a continuous single assembly of beams that includes attachment beams to the substrate and attachment beams to the masses,
wherein the continuous single assembly of beams also includes a junction beam that undergoes deformation according to oscillation of the masses, extending along a closed line to which the attachment beams to the substrate and the attachment beams to the masses are connected.
15: A resonator according to claim 14, wherein the junction beam extends over a curved line.
16: A resonator according to claim 14, wherein the junction beam surrounds the masses, which are in a form of half-moons that have rectilinear sides opposite each other and curved sides opposite the junction beam.
17: A resonator according to claim 14, wherein the attachment beams to the substrate include anchorage beams that extend overall in a direction of alignment of the masses between two regions of attachment to the substrate, which are perpendicular to the anchorage beams and joined to the anchorage beams at mid-distance from the regions of attachment.
18: A resonator according to claim 16, wherein the junction beam surrounds the masses, and the means for making the masses oscillate includes elements for producing oscillation located between the junction beam and the masses.
19: A resonator according to claim 14, wherein the substrate includes a decoupling frame that surrounds the masses, the means for making the masses oscillate, and the suspension beams and the coupling beams, and said decoupling frame being fixed to an underlying portion of the substrate by two frame anchorage regions aligned in a principal direction of oscillation of the masses.
20: A resonator according to claim 19, wherein the attachment beams to the masses are aligned with the frame anchorage regions.
21: A resonator according to claim 20, wherein the frame and the junction beam are configured to form end-stops in front of the frame anchorage regions and the oscillating masses possess opposite sides configured to form a mutual end stop.
22: A resonator according to claim 18, wherein the masses extend between the means for making the masses oscillate and possess opposite sides between them said masses equipped with interlocking electric combs.
23: A resonator according to claim 14, wherein the masses each include two-sub-masses placed symmetrically along a principle direction of oscillation of the masses, and the coupling beams include, for each mass, a sub-assembly of beams that extends between the sub-masses and that include two beams respectively linked to the sub-masses and to an interconnecting beam with the two beams connected to the sub-masses extending along a principal direction of oscillation of the masses.
24: A resonator according to claim 14, further comprising electrodes for measuring capacitance with the masses, the electrodes being fixed to the substrate and arranged in mass housings and being asymmetric along a direction of oscillation of the masses.
25: A resonator according to claim 14, wherein the means for making the masses oscillate includes interlocking toothed combs that exhibit an overlap length that is greater than an oscillation amplitude of the oscillating masses.
26: A resonator according to claim 22, wherein the interlocking electrical combs have teeth with a total mass equal to a total mass of extensions present on a face opposite the teeth of each oscillating mass.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for manufacturing an integrated circuit package system comprising:
connecting a carrier and an integrated circuit, mounted thereover, by a bond wire;
preforming a penetrable wire-in-film encapsulation having a cavity with orthogonal sidewalls;
pressing the penetrable wire-in-film encapsulation over the carrier, the bond wire, and the integrated circuit with the sidewalls of the cavity having a characteristic of an intersecting bulge caused by compression and the cavity exposing a portion of the integrated circuit; and
curing the penetrable wire-in-film encapsulation.
2. The method as claimed in claim 1 wherein preforming the penetrable wire-in-film encapsulation having the cavity includes attaching the penetrable wire-in-film encapsulation to a stiffener.
3. The method as claimed in claim 1 wherein preforming the penetrable wire-in-film encapsulation having the cavity includes preforming a penetrable film adhesive having a B-stage characteristic.
4. previously presented) The method as claimed in claim 1 further comprising mounting a device over the integrated circuit and in the cavity of the penetrable wire-in-film encapsulation.
5. The method as claimed in claim 1 further comprising attaching a lid over the cavity and the integrated circuit.
6. A method for manufacturing an integrated circuit package system comprising:
connecting a carrier and an integrated circuit, mounted thereover, by a bond wire;
preforming a penetrable wire-in-film encapsulation having a cavity with orthogonal sidewalls;
pressing the penetrable wire-in-film encapsulation over the carrier, the bond wire, and the integrated circuit with the sidewalls of the cavity having a characteristic of an intersecting bulge caused by compression and the cavity exposing a bond pad of the integrated circuit;
curing the penetrable wire-in-film encapsulation; and
attaching an external interconnect below the carrier.
7. The method as claimed in claim 6 wherein connecting the carrier and the integrated circuit includes connecting a substrate and an integrated circuit die.
8. The method as claimed in claim 6 wherein connecting the carrier and the integrated circuit includes connecting the carrier and a flip chip.
9. The method as claimed in claim 6 wherein connecting the carrier and the integrated circuit includes connecting the carrier and an inter-stacking module.
10. The method as claimed in claim 6 further comprising attaching a lid over the cavity and an optical area of the integrated circuit.
11. An integrated circuit package system comprising:
a carrier;
an integrated circuit over the carrier;
a bond wire connecting the carrier to the integrated circuit; and
a preformed penetrable wire-in-film encapsulation having a cavity with sidewalls over the carrier, the bond wire, and the integrated circuit with the sidewalls of the cavity having a characteristic of an intersecting bulge caused by compression and exposing a portion of the integrated circuit.
12. The system as claimed in claim 11 further comprising an electrical interconnect between the integrated circuit and the carrier.
13. The system as claimed in claim 11 wherein the penetrable wire-in-film encapsulation includes a penetrable film adhesive having a B-stage characteristic.
14. The system as claimed in claim 11 further comprising a device over the integrated circuit and in the cavity of the penetrable wire-in-filmencapsulation.
15. The system as claimed in claim 11 further comprising attaching a lid over the cavity and the integrated circuit.
16. The system as claimed in claim 11 wherein:
the integrated circuit includes a bond pad;
the penetrable wire-in-film encapsulation exposes the bond pad through the cavity; and
further comprising an external interconnect attached below and to the carrier.
17. The system as claimed in claim 16 wherein:
the carrier includes a substrate; and
the integrated circuit includes an integrated circuit die.
18. The system as claimed in claim 16 wherein the integrated circuit includes a flip chip.
19. The system as claimed in claim 16 wherein the integrated circuit includes an inter-stacking module.
20. The system as claimed in claim 16 further comprising a lid over the cavity and an optical area of the integrated circuit.