1. A memory circuit, comprising:
a sector including a memory location having a memory cell and a complementary memory cell; and
a sense amplifier circuit configured to:
determine a value stored in the memory location during a first read mode, and
determine a first state of the memory cell and a second state of the complementary memory cell during a second read mode.
2. The memory circuit of claim 1, wherein:
the memory cell includes a non-volatile memory cell; and
the complementary memory cell includes a complementary non-volatile memory cell.
3. The memory circuit of claim 1, wherein the sense amplifier is configured to determine the value stored in the memory location in response to a first state of the memory cell and a second state of the complementary memory cell.
4. The memory circuit of claim 1, wherein the sense amplifier circuit is configured to determine the value stored in the memory location in response to a difference between a first state of the memory cell and a second state of the complementary memory cell.
5. The memory circuit of claim 1, wherein the sense amplifier circuit is configured to determine the value stored in the memory location in response to a difference between a first voltage stored by the memory cell and a second voltage stored by the complementary memory cell.
6. The memory circuit of claim 1, wherein the sense amplifier circuit is configured to determine the first state of the memory cell and the second state of the complementary memory cell by reading the memory cell independently of the complementary memory cell.
7. The memory circuit of claim 1, wherein the sense amplifier circuit is configured to determine the first state of the memory cell and the second state of the complementary memory cell by reading the complementary memory cell independently of the memory cell.
8. The memory circuit of claim 1, further comprising:
wherein the sector includes a plurality of other memory locations in addition to the memory location, each of the other memory locations including a respective other memory cell and a respective other complementary memory cell;
wherein the sense amplifier circuit is configured to determine the states of the memory cell, complementary memory cell, the other memory cells, and the other complementary memory cells; and
a controller circuit configured to determine a number of the states that include a particular state, and to determine a state of the sector in response to the number.
9. The memory circuit of claim 8, wherein the particular state includes an erased state.
10. The memory circuit of claim 8, wherein the particular state includes a programmed state.
11. The memory circuit of claim 1, further comprising:
wherein the sector includes a plurality of other memory locations in addition to the memory location, each of the other memory locations including a respective other memory cell and a respective other complementary memory cell;
wherein the sense amplifier circuit is configured to determine the states of the memory cell, complementary memory cell, the other memory cells, and the other complementary memory cells; and
a controller circuit configured to determine a number of the states that include a particular state, and to determine that the state of the sector includes the particular state if the number of states is below a threshold.
12. The memory circuit of claim 1, further comprising:
wherein the sector includes a plurality of other memory locations in addition to the memory location, each of the other memory locations including a respective other memory cell and a respective other complementary memory cell;
wherein the sense amplifier circuit is configured to determine the states of the memory cell, complementary memory cell, the other memory cells, and the other complementary memory cells; and
a controller circuit configured to determine a number of the states that include a particular state, and to determine that the state of the sector includes a state opposite to the particular state if the number of states is above a threshold.
13. The memory circuit of claim 1, further comprising:
wherein the sector includes a plurality of other memory locations in addition to the memory location, each of the other memory locations including a respective other memory cell and a respective other complementary memory cell;
wherein the sense amplifier circuit is configured to determine the states of the memory cell, complementary memory cell, other memory cells, and other complementary memory cells; and
a controller circuit configured to determine a number of the states that include a particular state, and to determine that the state of the sector includes a written state if the number of states is between two thresholds.
14. The memory circuit of claim 1, further comprising:
wherein the sector includes a plurality of other memory locations in addition to the memory location, each of the other memory locations including a respective other memory cell and a respective other complementary memory cell;
wherein the sense amplifier circuit is configured to determine the states of the memory cell, complementary memory cell, other memory cells, and other complementary memory cells; and
a controller circuit configured to determine a number of the states that include a particular state, to determine a state of the sector in response to the number, and, if the determined state of the sector is not an erased state, then to erase the memory cell, complementary memory cell, other memory cells and other complementary memory cells, and to program the memory cell, complementary memory cell, other memory cells and other complementary memory cells.
15. The memory circuit of claim 1, further comprising:
wherein the sector includes a plurality of other memory locations in addition to the memory location, each of the other memory locations including a respective other memory cell and a respective other complementary memory cell;
wherein the sense amplifier circuit is configured to determine the states of the memory cell, complementary memory cell, other memory cells, and other complementary memory cells; and
a controller circuit configured to determine a number of the states that include a particular state, to determine a state of the sector in response to the number, and, if the determined state of the sector is not an erased state, then to erase the memory cell, complementary memory cell, other memory cells and other complementary memory cells, to program the memory cell, complementary memory cell, other memory cells and other complementary memory cells, and to write data to at least one of the memory cell, complementary memory cell, other memory cells, and other complementary memory cells.
16. A memory circuit, comprising:
a plurality of sectors of memory cells,
wherein each memory cell is configured to take a programmed state or an erased state,
the memory cells each including a direct memory cell and a complementary memory cell,
a read circuit configured to select at least one of the sectors, determine a number of memory cells in the selected sector that are in the programmed state, determine a number of memory cells in the selected sector that are in the erased state, and identify a condition of the selected sector according to a comparison between the number of memory cells in the programmed state and the number of memory cells in the erased state.
17. The memory circuit of claim 16, wherein said identified condition is one of:
a non-written condition when the memory cells are in equal states; and
a written condition wherein the memory cells are in different states.
18. The memory circuit of claim 16, wherein the read circuit includes a comparison circuit configured to compare electrical quantities associated with a least part of the memory cells in the selected sector to a threshold value.
19. The memory circuit of claim 17, wherein the read circuit identifies the selected sector as not in the non-written condition when the number of memory cells of the selected sector in a given state exceeds a limit value.
20. The memory circuit of claim 19, wherein the read circuit includes a counting circuit configured to count the memory cells of the selected sector in the given state and wherein counting is stopped when the number of memory cells of the selected sector in the given state exceeds the limit value.
21. The memory circuit of claim 17, wherein the read circuit identifies the selected sector as in the written condition when a predetermined subset of locations in the selected sector stores a predetermined sequence of logic values.
22. The memory circuit of claim 16, further comprising:
a select circuit configured to select one of the sectors in response to a received command; and
a control circuit configured, if the selected sector is identified as in the written condition, to bring all the memory cells of the selected sector into the programmed state and then bring all the memory cells of the selected sector from the programmed state to the erased state.
23. The memory of claim 16, further comprising:
a select circuit configured to select one of the sectors in response to a writing instruction of a word in the selected sector, the word comprising a target logic value of each location of the selected sector; and
a control circuit configured, if the selected sector is identified as in the written condition, to bring all the memory cells of the selected sector into the programmed state, and then bring all the memory cells of the selected sector from the programmed state to the erased state, and then bring each direct memory cell of the selected sector into the state corresponding to the respective target logic value, and bring each complementary memory cell of the selected sector into the state corresponding to the complement of the respective target logic value.
24. The memory of claim 16, further comprising:
a select circuit configured to select one of the sectors; and
a control circuit configured, if the selected sector is identified as in the non-written condition with the memory cells in the programmed state, to bring all the memory cells of the selected sector into the erased state.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A rock cutting assembly of the type mounted to a machine capable of exerting downward force, said assembly comprising:
a plurality of cutters;
a plurality of cylinders, each of said cylinders supporting at least one of said cutters;
wherein each of said cylinders comprise a hydraulic cylinder for distributing the downward force exerted from the machine.
2. The assembly of claim 1, further including:
an assembly frame pivotally supporting each of said cylinders; and
a caster pivotally affixing said assembly frame to the machine for allowing said assembly to pivot in a substantially horizontal plane.
3. An assembly as set forth in claim 2 wherein said assembly frame includes a plurality of pins affixed thereto for pivotally attaching said cylinders to said frame and allowing the cylinder to pivot in a substantially vertical plane.
4. An assembly as set forth in claim 1, wherein each of said cutters includes a cutter wheel.
5. An assembly as set forth in claim 6, wherein each of said cutters includes a cutter frame for pivotally supporting said cutter wheel.
6. An assembly as set forth in claim 5, wherein said assembly includes a plurality of support arm pairs, each of said support arm pairs having one of said cutter frames fixedly attached therebetween.
7. An assembly as set forth in claim 6, wherein each of said support arm pairs is pivotally attached to said assembly frame at an opposite end thereof from said cutter frames.
8. An assembly as set forth in claim 6, wherein said plurality of support arm pairs include at least first pair and a second pair, said first pair disposed between said second pair.
9. An assembly as set forth in claim 8, wherein said first support arm pair and said second support arm pair include an identical pivot axis.
10. An assembly as set forth in claim 9, wherein said first support arm pair pivots independently of said second support arm pair.
11. An assembly as set forth in claim 1, wherein each of said cylinders is in communication with a hydraulic fluid circuit, said hydraulic fluid circuit supplying hydraulic pressure evenly to each said cylinder.
12. An assembly as set forth in claim 1, wherein said plurality of cutters is arranged in a sequential pattern oriented longitudinally with the machine cutting path.
13. An assembly as set forth in claim 12, wherein each of said cutter wheels is arranged in an offset spatial relationship for altering the distance between the cutter paths.
14. An assembly as set forth in claim 1, wherein said assembly includes a single cylinder independently supporting each of said plurality of cutters.
15. A rock cutting assembly comprising:
a plurality of cutters;
a plurality of cylinders, each supporting at least one of said cutters;
an assembly frame supporting said cylinders; and
said cylinders being in communication with a hydraulic circuit for providing downward force to said cutters.
16. An assembly as set forth in claim 15, further including:
a caster pivotally supporting said assembly frame allowing said assembly frame to pivot in a substantially horizontal plane.
17. An assembly as set forth in claim 15, wherein said at least one cutter includes a cutter wheel.
18. An assembly as set forth in claim 16, wherein said assembly includes at least one support arm pair, said at least one support arm pair having at least one of said cutters fixedly attached therebetween.
19. An assembly as set forth in claim 18, wherein said at least one support arm pair is pivotally attached to said assembly frame.
20. An assembly as set forth in claim 19, wherein said at least one support arm pair is disposed between a second support arm pair.
21. An assembly as set forth in claim 20, wherein said first support arm pair and said second support arm pair include a common pivot axis.
22. An assembly as set forth in claim 15, wherein said cutters are arranged in an offset spatial relationship along a longitudinal cutting path.