what is claimed is:
1. A data processing device comprising:
means which maps a program that rewrites a data storage region in a nonvolatile memory in an address space of a CPU in a case when the data storage region within the non-volatile memory is rewritten, and does not map the program in the address space of the CPU in other cases.
2. A data processing device comprising:
a CPU;
a rewritable non-volatile memory including a program storage region that stores first and second programs to be executed by the CPU, and a data storage region that stores data to be accessed by the CPU;
a ROM that stores a third program to be executed by the CPU;
a RAM that is mapped in a first address range in an address space of the CPU; and
an address decoder which is equipped with a flag register, and maps the nonvolatile memory in a second address range in the address space of the CPU when the flag resister is in a first state and maps the ROM in the second address range in the address space of the CPU and maps the data storage region of the non-volatile memory in a third address range in the address space of the CPU when the flag resister is in a second state,
wherein the first program stored in the non-volatile memory includes a routine to transfer the second program stored in the non-volatile memory to the RAM, and to branch to a head address of the second program transferred to the RAM,
wherein the second program stored in the non-volatile memory includes a routine to set the flag resister of the address decoder to the second state, to call the third program stored in the ROM as a sub-routine, and to set the flag resister of the address decoder to the first state, and
wherein the third program stored in the ROM includes a routine to write data stored in the RAM in the data storage region of the non-volatile memory that is mapped to the third address range.
3. The data processing device according to claim 2, wherein the data processing device is a single-chip microcomputer.
4. A method of controlling a data processing device comprising:
a step of mapping a program that rewrites a data storage region in a non-volatile memory in an address space of a CPU, in a case when the data storage region within the non-volatile memory is rewritten, and not mapping the program in the address space of the CPU in other cases.
5. A method of controlling a data processing device, wherein the data processing device comprises:
a CPU;
a rewritable non-volatile memory including a program storage region that stores first and second programs to be executed by the CPU, and a data storage region that stores data to be accessed by the CPU;
a ROM that stores a third program to be executed by the CPU;
a RAM that is mapped in a first address range in an address space of the CPU; and
an address decoder,
wherein the method comprises a step of mapping the non-volatile memory in a second address range in the address space of the CPU when the flag resister is in a first state, and mapping the ROM in the second address range in the address space of the CPU and maps the data storage region of the non-volatile memory in a third address range in the address space of the CPU when the flag resister is in a second state,
wherein the first program stored in the non-volatile memory includes a routine to transfer the second program stored in the non-volatile memory to the RAM, and to branch to a head address of the second program transferred to the RAM,
wherein the second program stored in the non-volatile memory includes a routine to set the flag resister of the address decoder to the second state, to call the third program stored in the ROM as a sub-routine, and to set the flag resister of the address decoder to the first state, and
wherein the third program stored in the ROM includes a routine to write data stored in the RAM in the data storage region of the non-volatile memory that is mapped to the third address range.
6. The method of controlling data processing device according to claim 5,
wherein the data processing device is a single-chip microcomputer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of establishing a communication link in an ADSL system using a bearer channel and latency mode when transmittingreceiving initialization messages and transmittingreceiving the initialization messages by using message tones and backup tones, the method comprising:
(a) receiving the initialization messages from the message tones and the backup tones;
(b) performing a bit masking operation on the initialization messages of the message tones and the backup tones to remove first errors thereof;
(c) correcting second errors of one of the initialization messages of the message tones and the backup tones of which the first errors are bit-masked in the step (b);
(d) performing a cyclic redundancy check operation on the initialization message having the corrected second errors to check for uncorrected second errors; and
(e) determining link establishment or link failure of the communication link on which the initialization messages are transmitted based on the result of the cyclic redundancy check of the step (d).
2. The method according to claim 1, wherein the method further comprises a step (f), wherein, after performing the bit masking operation, detecting the second errors, the second errors having different byte values in the initialization messages in the message tones and the backup tones by performing a predetermined logic operation, and utilizing the number of the detected second errors as a repetition number of the cyclic redundancy check operation of the step (d).
3. The method according to claim 2, wherein the logic operation of the step (f) includes an exclusive-OR operation.
4. The method according to claim 2, wherein the errors in the step (b) occur due to a crosstalk or noise on the communication link.
5. The method according to claim 2, wherein, in a case where the number of the errors detected in the step (f) is 3, at least one error out of the three errors is changed by the error correction performed in the step (c).
6. The method according to claim 2, wherein the initialization messages corrected in the step (c) are initialization messages having a few errors.
7. The method according to claim 3, wherein the step (b) comprises a step of receiving the initialization message from the message tones and the backup tones.
8. The method according to claim 7, wherein the step (f) comprises:
(f1) counting the number of the detected errors and setting the number to a count value; and
(f2) setting a reference count value to zero.
9. The method according to claim 8, wherein the step (e) comprises:
(e1) determining whether the number of the errors obtained by the cyclic redundancy check operation is zero;
(e2) when the number of the errors obtained by the cyclic redundancy check operation is determined to be zero in the step (e1), asserting that there is a link establishment in the ADSL system;
(e3) when the number of the errors obtained by the cyclic redundancy check operation is determined to be not zero in the step (e1), determining whether the reference count value is smaller than the set count value;
(e4) when the reference count value is determined to be not smaller than the set count value in the step (e3), asserting that there is a link failure in the ADSL system;
(e5) when the reference count value is determined to be smaller than the set count value in the step (e3), determining whether time associated with the set count value is longer than a link initialization time;
(e6) when the time associated with the set count value is determined to be longer than the link initialization time in the step (e5), proceeding to the step (e4) to assert that there is a link failure in the ADSL system; and
(e7) when the time associated with the set count value is determined to be not longer than the link initialization time in the step (e5), increasing the reference count value by one and providing the increased count value to the step (c).