1. A math operation practice and learning game comprising:
(a) a first set of cards each having at least one mathematical operation question thereon;
(b) a second set of cards each having at least one mathematical operation answer thereon that corresponds to at least one mathematical operation question on one of the cards in the first set of cards;
(c) a chart containing a list of the math operation answers which correspond to the math operation questions in the first set of cards;
(d) a timer device;
(e) a first flag having a first unique indicia thereon and being useable during game play to indicate when no cards in the second set of cards having a correct mathematical operation answer to a mathematical answer question on one of the first set of cards have been presented, and
(f) a second flag having a second unique indicia thereon and being useable during game play to indicate when an incorrect answer to a mathematical operation question on a card in the first set of cards has been given, wherein the object of the game is to be the first player to discard all of his or her cards in the second set of cards.
2. The math operation teaching game of claim 1 wherein said mathematical operation questions on said first set of cards are taken from the group consisting of addition, subtraction, multiplication and division.
3. The math operation teaching game of claim 2 wherein said mathematical operation questions on the first set of cards are related to multiplication.
4. The math operation teaching game of claim 2 wherein said mathematical operation questions are related to division.
5. The math operation teaching game of claim 2 wherein said mathematical functions are related to addition.
6. The math operation teaching game of claim 2 wherein said questions on the cards are related to subtraction.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of fabricating a semiconductor device, the method comprising:
forming an interlayer insulating layer on a semiconductor substrate;
forming a hard mask layer on the interlayer insulating layer;
forming a hard mask pattern in which a plurality of contact hole patterns are formed by patterning the hard mask layer at least two times;
conformally forming a supporting liner layer on the hard mask pattern, which supports the hard mask pattern during etching by reinforcing the thickness of the hard mask pattern;
forming a plurality of contact hole patterns in the interlayer insulating layer using the hard mask pattern on which the supporting liner layer is formed as an etching mask; and
forming contact plugs filling the plurality of contact hole patterns.
2. The method of claim 1, wherein the forming of the hard mask layer comprises forming a hard mask layer having a multi-layered structure on the interlayer insulating layer.
3. The method of claim 1, wherein the forming of the hard mask layer comprises forming a silicon oxide layer, a silicon nitride layer, a silicon oxy-nitride layer, or an amorphous carbon layer.
4. The method of claim 1, wherein the supporting liner layer is formed using atomic layer deposition (ALD) or plasma enhanced chemical vapor deposition (PECVD).
5. The method of claim 1, wherein the contact hole patterns are formed with a width of about 50 nm or less.
6. The method of claim 1, wherein the contact hole patterns are formed such that a distance between the contact hole patterns is about 50 nm or less.
7. The method of claim 1, wherein the forming of the hard mask pattern comprises:
forming a plurality of first contact hole patterns that are separated by a predetermined distance from each other by performing a first patterning process; and
forming second contact hole patterns between the first contact hole patterns by performing a second patterning process.
8. The method of claim 1, wherein the forming of the hard mask pattern comprises:
forming a first anti-reflective layer on the hard mask layer;
forming on the anti-reflective layer a first photoresist pattern that exposes the top of the anti-reflective layer and has the first contact hole pattern formed therein;
forming the plurality of first contact hole patterns separated by a predetermined distance in the hard mask layer using the first photoresist pattern as an etching mask;
removing the first photoresist pattern and the first anti-reflective layer, and forming a second anti-reflective layer covering the hard mask layer in which the first contact hole pattern is formed;
forming a second photoresist pattern that exposes the top of the second anti-reflective layer and in which the second contact hole patterns interspersed with the plurality of first contact hole patterns are formed; and
forming the second contact hole pattern in the hard mask layer in which the first contact hole patterns are formed using the second photoresist pattern as an etching mask.
9. A method of fabricating a semiconductor device, the method comprising:
forming an interlayer insulating layer on a semiconductor substrate;
forming a hard mask layer having a multi-layered structure on the interlayer insulating layer;
forming a top mask pattern layer in which a plurality of contact hole patterns are formed by patterning the top layer of the hard mask layer at least two times;
conformally forming on the top mask pattern layer a supporting liner layer that supports the top mask pattern layer during etching by reinforcing the thickness of the top mask patter layer;
completing the hard mask pattern having the multi-layered structure by patterning the top mask pattern layer in which the supporting liner layer is formed using an etching mask;
forming a plurality of contact hole patterns in the interlayer insulating layer using the hard mask pattern using an etching mask; and
forming contact plugs that fill the plurality of contact hole patterns.
10. The method of claim 9, wherein the forming of the hard mask layer comprises forming a silicon oxide layer, a silicon nitride layer, a silicon oxy-nitride layer, or an amorphous carbon layer.
11. The method of claim 9, wherein the forming of the supporting liner layer comprises forming the supporting liner layer using atomic layer deposition (ALD) or plasma enhanced chemical vapor deposition (PECVD).
12. The method of claim 9, wherein the forming of the contact hole patterns comprises forming the contact hole patterns with a width of about 50 nm or less.
13. The method of claim 9, wherein the forming of the contact hole patterns comprises forming the contact hole patterns such that a distance between the contact hole patterns is about 50 nm or less.
14. The method of claim 9, wherein the forming of the top mask pattern layer comprises:
forming a plurality of first contact hole patterns separated by a predetermined distance by performing a first patterning process on the top layer of the hard mask layer; and
forming second contact hole patterns between the plurality of first contact hole patterns by performing a second patterning process on the top layer of the hard mask layer in which the first contact hole patterns are formed.
15. The method of claim 9, wherein the forming of the top hard mask pattern comprises:
forming a first anti-reflective layer on the top layer of the hard mask layer;
forming on the first anti-reflective layer a first photoresist pattern that exposes the top of the first anti-reflective layer and in which the first contact hole patterns are formed;
forming the plurality of first contact hole patterns separated by a predetermined distance in the top layer of the hard mask layer using the first photoresist pattern as an etching mask;
removing the first photoresist pattern and the first anti-reflective layer;
forming a second anti-reflective layer covering the top layer of the hard mask layer in which the first contact hole patterns are formed;
forming a second photoresist pattern that exposes the top of the second anti-reflective layer and in which second contact hole patterns interspersed with the first contact hole patterns are formed; and
forming the second contact hole pattern in the top layer of the hard mask layer in which the first contact hole patterns are formed using the second photoresist pattern as an etching mask.