What is claimed is:
1. A frequency voltage converter comprising:
a first transmission line comprised of one signal line which branches off from a signal line for transmitting an input signal corresponding to a modulated wave signal;
a second transmission line comprised of the other signal line which branches off from said input signal transmitting signal line;
a mixer circuit having a first input terminal connected to said first transmission line and a second input terminal connected to said second transmission line;
a delay-amount variable first delay line circuit placed in said second transmission line between a portion where said first transmission line and said second transmission line branch off from each other and the second input terminal of said mixer circuit;
a third transmission line comprised of one signal line which branches of f from a signal line for transmitting a reference signal having a predetermined frequency;
a fourth transmission line comprised of the other signal line which branches off from said reference signal transmitting signal line;
a delay-amount variable second delay line circuit placed in said fourth transmission line between a portion where said third transmission line and said fourth transmission line branch off from each other and a portion where said third transmission line and said fourth transmission line are joined to each other; and
delay amount control means connected to said third transmission line, said fourth transmission line, a control section of said first delay line circuit and a control section of said second delay line circuit and for outputting the same control signal to the control section of said second delay line circuit and the control section of said first delay line circuit so that the reference signal passing through said fourth transmission line is delayed by a predetermined cycle with respect to the reference signal passing through said third transmission line.
2. The frequency voltage converter according to claim 1, wherein said first delay line circuit comprises a plurality of stages of unit delay circuits, said second delay line circuit comprises a plurality of stages of unit delay circuits, and the unit delay circuits constituting said first delay line circuit and the unit delay circuits constituting the second delay line circuit respectively have the same circuit configuration.
3. The frequency voltage converter according to claim 2, wherein when the number of stage of the unit delay circuits series-connected in said first delay line circuit, the number of stage of the unit delay circuits series-connected in said second delay line circuit, the center frequency of the input signal, and the frequency of the reference signal are respectively defined as a, b, fc and fr, the numbers of stage for said first delay line circuit and said second delay line circuit are respectively set so that abfr4fc is established, and the frequency of the reference signal is adjusted.
4. The frequency voltage converter according to claim 2, wherein when the number of stages of the unit delay circuits series-connected in said first delay line circuit, the number of stages of the unit delay circuits series-connected in said second delay line circuit, the center frequency of the input signal, and the frequency of the reference signal are respectively defined as a, b, fc and fr, the numbers of the stages for said first delay line circuit and said second delay line circuit are respectively set so that abfr2fc is established, and the frequency of the reference signal is adjusted.
5. The frequency voltage converter according to claim 2, further including:
a first buffer and a second buffer disposed in order from the side close to the branch portion between the branch portion and the first input terminal of said mixer circuit in said first transmission line,
a third buffer disposed between the branch portion and said first delay line circuit in said second transmission line,
a fourth buffer disposed between said first delay line circuit and the second input terminal of said mixer circuit in said second transmission line,
a fifth buffer and a sixth buffer disposed in order from the side close to the branch portion between the branch portion and the joined portion in said third transmission line,
a seventh buffer disposed between the branch portion and said second delay line circuit in said fourth transmission line, and
an eighth buffer disposed between said second delay line circuit and the joined portion in said fourth transmission line,
wherein said first buffer, said third buffer, said fifth buffer and said seventh buffer respectively have the same circuit configuration as an output buffer of said each unit delay circuit, and said second buffer, said fourth buffer, said sixth buffer and said eighth buffer respectively have the same circuit configuration as an input buffer of said each unit delay circuit.
6. A frequency voltage converter comprising:
a first transmission line comprised of one signal line which branches off from a signal line for transmitting an input signal corresponding to a modulated wave signal;
a second transmission line comprised of the other signal line which branches off from said input signal transmitting signal line;
a mixer circuit having a first input terminal connected to said first transmission line and a second input terminal connected to said second transmission line;
a delay-amount variable delay line circuit placed in said second transmission line between a portion where said first transmission line and said second transmission line branch off from each other and the second input terminal of said mixer circuit;
a signal line for transmitting a reference signal having a predetermined frequency;
a ring oscillator capable of varying an oscillation frequency; and
delay amount control means connected to the signal line for transmitting the reference signal, a signal line for transmitting a signal outputted from said ring oscillator, and a control section of said delay line circuit and a control section of said ring oscillator and for outputting the same control signal to the control section of said ring oscillator and the control section of said delay line circuit so that the frequency of the signal outputted from said ring oscillator coincides with that of the reference signal,
wherein said delay line circuit comprises a plurality of stages of unit delay circuits, said ring oscillator comprises a plurality of stages of unit delay circuits disposed in ring form, and the unit delay circuits constituting said delay line circuit and the unit delay circuits constituting said ring oscillator respectively have the same circuit configuration.
7. A frequency voltage converter comprising:
a first transmission line comprised of one signal line which branches off from a signal line for transmitting an input signal corresponding to a modulated wave signal;
a second transmission line comprised of the other signal line which branches off from said input signal transmitting signal line;
a mixer circuit having a first input terminal connected to said first transmission line and a second input terminal connected to said second transmission line;
a delay-amount variable delay line circuit placed in said second transmission line between a portion where said first transmission line and said second transmission line branch off from each other and the second input terminal of said mixer circuit;
a signal line for transmitting a reference signal having a predetermined frequency;
a ring oscillator capable of varying an oscillation frequency;
a divider for inputting a signal outputted from said ring oscillator; and
delay amount control means connected to the signal line for transmitting the reference signal, a signal line for transmitting a signal outputted from said divider, and a control section of said delay line circuit and a control section of said ring oscillator and for outputting the same control signal to the control section of said ring oscillator and the control section of said delay line circuit so that the frequency of the signal outputted from said divider coincides with that of the reference signal,
wherein said delay line circuit comprises a plurality of stages of unit delay circuits, said ring oscillator comprises a plurality of stages of unit delay circuits disposed in ring form, and the unit delay circuits constituting said delay line circuit and the unit delay circuits constituting said ring oscillator respectively have the same circuit configuration.
8. The frequency voltage converter according to claim 2, wherein each of delay-amount variable delay element circuits which are connected and provided by a predetermined number within said each unit delay circuit so as to constitute said unit delay circuit, is a differential circuit provided with current amount control means and output amplitude control means.
9. The frequency voltage converter according to claim 2, wherein each of delay-amount variable delay element circuits which are connected and provided by a predetermined number within said each unit delay circuit so as to constitute said unit delay circuit, is configured so that amount-of -current control means are connected in series with CMOS inverter circuits.
10. The frequency voltage converter according to claim 2, wherein a phase detector having a first input terminal connected to said first transmission line and a second input terminal connected to said second transmission line is disposed in place of said mixer circuit.
11. The frequency voltage converter according to claim 10, wherein said phase detector is a phase detecting circuit for detecting only delayed phase.
12. The frequency voltage converter according to claim 6, wherein each of delay-amount variable delay element circuits which are connected and provided by a predetermined number within said each unit delay circuit so as to constitute said unit delay circuit, is a differential circuit provided with current amount control means and output amplitude control means.
13. The frequency voltage converter according to claim 6, wherein each of delay-amount variable delay element circuits which are connected and provided by a predetermined number within said each unit delay circuit so as to constitute said unit delay circuit, is configured so that amount-of-current control means are connected in series with CMOS inverter circuits.
14. The frequency voltage converter according to claim 6, wherein a phase detector having a first input terminal connected to said first transmission line and a second input terminal connected to said second transmission line is disposed in place of said mixer circuit.
15. The frequency voltage converter according to claim 14, wherein said phase detector is a phase detecting circuit for detecting only delayed phase.
16. The frequency voltage converter according to claim 7, wherein each of delay-amount variable delay element circuits which are connected and provided by a predetermined number within said each unit delay circuit so as to constitute said unit delay circuit, is a differential circuit provided with current amount control means and output amplitude control means.
17. The frequency voltage converter according to claim 7, wherein each of delay-amount variable delay element circuits which are connected and provided by a predetermined number within said each unit delay circuit so as to constitute said unit delay circuit, is configured so that amount-of-current control means are connected in series with CMOS inverter circuits.
18. The frequency voltage converter according to claim 7, wherein a phase detector having a first input terminal connected to said first transmission line and a second input terminal connected to said second transmission line is disposed in place of said mixer circuit.
19. The frequency voltage converter according to claim 18, wherein said phase detector is a phase detecting circuit for detecting only delayed phase.
20. The frequency voltage converter according to claim 2, wherein when the number of stage of the unit delay circuits series-connected in said first delay line circuit, the number of stage of the unit delay circuits series-connected in said second delay line circuit, the center frequency of the input signal, and the frequency of the reference signal are respectively defined as a, b, fc and fr, the numbers of stage for said first delay line circuit and said second delay line circuit are respectively set so that ab3fr4fc or 3fr2fc is established, and the frequency of the reference signal is adjusted.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of handling secure data in a secure system, wherein the secure data is passed between a processor and memory external to the processor, comprising:
maintaining, in an encrypted form in the external memory, a set of metadata used to encrypt and decrypt the secure data;
maintaining, in a decrypted form in a cache internal to the processor, a limited subset of the metadata;
receiving a request to access a block of the secure data;
retrieving the block of secure data from the external memory in encrypted form;
determining whether a first portion of metadata needed to decrypt the block of secure data is in the cache;
when the first portion of metadata is not in the cache:
retrieving the first portion of metadata from the external memory;
determining whether a second portion of metadata is in the cache; and
when the second portion is not in the cache, retrieving the second portion of metadata from the external memory and decrypting the second portion of metadata using a third portion of metadata maintained in the cache;
decrypting the first portion of metadata using the second portion of metadata in the cache; and
decrypting the block of secure data using the first portion of metadata.
2. The method of claim 1, further comprising, when the first portion of metadata is in the cache:
calculating an address corresponding to a location of the first portion of metadata in the external memory; and
examining one or more tag ram entries for a match with the calculated address.
3. The method of claim 1, further comprising:
retrieving a portion of metadata from the external memory and decrypting the portion of metadata using metadata maintained in hardware on the processor.
4. The method of claim 1, further comprising:
validating the block of secure data by comparing an integrity value calculated on the secure block of data with an integrity value contained in the first portion of metadata.
5. The method of claim 4, further comprising:
placing a copy of the secure block of data in the cache; and
modifying the block of secure data in the cache without writing the block of secure data to the external memory until a cache line containing the block of secure data is cast out.
6. The method of claim 5, further comprising receiving a memory access request requiring the cache line containing the block of secure data to be cast out and, prior to casting the cache line out:
updating a security version value contained in the first portion of metadata;
updating an integrity value contained in the first portion of data based on the modified block of secure data;
encrypting the modified block of secure data using the updated security version value; and
writing the modified block of secure data to the external memory in encrypted form.
7. A method of handling secure data in a secure system, wherein the secure data is passed between a processor and memory external to the processor, comprising:
maintaining, in the external memory in an encrypted form, an authentication tree containing a first level of metadata comprising security version values for use in encrypting blocks of secure data and integrity values for use in authenticating blocks of secure data encrypted using the security version values and at least a second level containing security version values for use in encrypting portions of the first level of metadata;
maintaining, in external memory, blocks of secure data encrypted using the security version values contained in the first level of metadata;
maintaining, in a decrypted form in a cache internal to the processor, a limited subset of the authentication tree spanning multiple levels;
maintaining blocks of secure data in the cache; and
modifying a block of secure data in the cache without writing the block of secure data to the external memory until a cache line containing the block of secure data is cast out.
8. The method of claim 7, wherein modifying the block of secure data in the cache comprises modifying the block of secure data multiple times before writing the block of secure data to the external memory.
9. The method of claim 7, further comprising:
receiving a request to access secure data;
determining whether the requested secure data is contained in the cache; and when the requested secure data is contained in the cache, returning the secure data from the cache without accessing the external memory.
10. The method of claim 9, further comprising, when the requested secure data is not contained in the cache:
determining whether first metadata required to decrypt a block of secure data containing the requested data is contained in the first level of metadata maintained in the cache; and
when the first level metadata is maintained in the cache, retrieving the block of secure data containing the requested data and decrypting the block of secure data using the first level metadata.
11. The method of claim 10, further comprising when first metadata required to decrypt a block of secure data containing the requested data is not contained in the first level of metadata maintained in the cache:
determining whether second metadata required to decrypt a block of data containing the first metadata is contained in a second level of metadata maintained in the cache; and
when the second metadata is maintained in the cache, retrieving the block of data containing the first metadata and decrypting the block of data containing the first metadata using the second metadata.
12. The method of claim 10, further comprising initiating a read of the secure block of data prior to completion of decrypting the block of data containing the first metadata.
13. The method of claim 7, further comprising:
modifying at least one of data or metadata maintained in the cache without writing blocks of data containing the modified data or metadata to external memory until cache lines containing the blocks of modified data or metadata are cast out.
14. A method of handling secure data in a secure system, wherein the secure data is passed between a processor and memory external to the processor, comprising:
maintaining, in an encrypted form in the external memory, a set of metadata used to encrypt and decrypt the secure data;
maintaining, in a decrypted form in a cache internal to the processor, a limited subset of the metadata;
receiving a request to access a block of the secure data;
retrieving the block of secure data from the external memory in encrypted form;
determining when a first portion of metadata needed to decrypt the block of secure data is in the cache;
when the first portion of metadata is not in the cache:
retrieving the first portion of metadata from the external memory;
determining whether a second portion of metadata is in the cache; and
when the second portion is not in the cache, retrieving the second portion of metadata from the external memory and decrypting the second portion of metadata using a third portion of metadata maintained in the cache;
decrypting the first portion of metadata using the second portion of metadata; and
decrypting the block of secure data using the first portion of metadata in the cache, wherein:
(i) the first portion of metadata comprises one or more security version values used to affect encryption of secure data and one or more integrity values used to authenticate secure data encrypted using the one or more security version values; and
(ii) the second portion of metadata comprises one or more security version values used to affect encryption of the first portion of metadata.