What is claimed is:
1. A dual-use visible-lightinfrared image pickup device including an image pickup element having sensitivity ranging from the visible-light range to the infrared range and means for correcting a shift in focal point, which would otherwise be caused by longitudinal chromatic aberration arising in a photographing lens, the device comprising:
a variable-thickness optical filter interposed between a photographing lens system and said image pickup element of solid state;
an actuator for changing the thickness of said variable-thickness optical filter;
memory for storing a correlation table defining the correlation between said photographing conditions and the thickness of said variable-thickness optical filter which can correct said shift in optical point; and
thickness control means for controlling said actuator on the basis of said correlation table stored in said memory.
2. The dual-use visible-lightinfrared image pickup device according to claim 1, wherein said variable-thickness optical filter is formed from two wedge-shaped prisms combined together to form a parallel-plane plate, and the overall thickness of said variable-thickness optical filter can be changed, by means of moving said prisms in opposite directions while oblique lines of said prisms remain in contact with each other.
3. The dual-use visible-lightinfrared image pickup device according to claim 1, wherein said variable-thickness optical filter is constructed such that the overall thickness of said variable-thickness optical filter can be changed by means of shifting liquid filled in the space defined between the two parallel plates.
4. The dual-use visible-lightinfrared image pickup device according to claim 1, wherein the photographing conditions correspond to at least one of the wavelength of incident light, the brightness of said photographing lens system, the brightness of a subject, a zoom magnification, a focal point, and the aperture of a diaphragm.
5. The dual-use visible-lightinfrared image pickup device according to claim 1, wherein said photographing lens is a zoom lens.
6. The dual-use visible-lightinfrared image pickup device according to claim 1, wherein said photographing lens is a fixed-focus lens.
7. The dual-use visible-lightinfrared image pickup device according to claim 1, wherein said image pickup device is a monitoring camera.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of fabricating an on-chip capacitor having a variable capacitance, the method comprising:
forming first and second ports in a dielectric layer that are configured to be powered with opposite polarities;
forming first and second electrodes in the dielectric layer;
forming a first voltage-controlled unit configured to selectively couple the first electrode with the first port; and
forming a second voltage-controlled unit configured to selectively couple the second electrode with the second port;
wherein the on-chip capacitor has a larger capacitance value when the first electrode is coupled by the first voltage-controlled unit with the first port and the second electrode is coupled by the second voltage-controlled unit with the second port.
2. The method of claim 1 wherein the on-chip capacitor is carried by a back-end-of-line (BEOL) wiring structure on a chip, and further comprising:
fabricating an integrated circuit on the chip that is electrically coupled with the first and second ports.
3. The method of claim 2 wherein the first and second voltage-controlled units are first and second field effect transistors of the integrated circuit fabricated on the chip.
4. The method of claim 3 wherein forming the first and second voltage-controlled units further comprises:
fabricating the first and second field effect transistors on the chip; and
forming conductive features configured to concurrently supply a control voltage to a first gate stack of the first field effect transistor and to a second gate stack of the second field effect transistor to simultaneously connect the first electrode with the first port and the second electrode with the second port and provide the larger capacitance value.
5. The method of claim 2 wherein the on-chip capacitor is configured to be switched between the first and second voltage-controlled units while the integrated circuit is operating.
6. The method of claim 1 further comprising:
forming a third electrode in the dielectric layer that is directly connected with the first port; and
forming a fourth electrode in the dielectric layer that is directly connected with the second port,
wherein the third and fourth electrodes providing a fixed capacitance that is increased when the first and second voltage-controlled units are in the second state.
7. The method of claim 6 wherein the first, second, third, and fourth electrodes are formed with a juxtaposed arrangement, and the first electrode is separated from the second electrode by the third and fourth electrodes.
8. The method of claim 7 wherein the first and second electrodes are formed with a symmetrical arrangement on opposite sides of the third and fourth electrodes.
9. The method of claim 6 wherein the on-chip capacitor is integrated into one or more metallization levels of a back-end-of-line (BEOL) wiring structure, and the third and fourth electrodes are formed in a different metallization level than the first and second electrodes.
10. The method of claim 1 wherein the first and second electrodes are disposed in a first metallization level of a multi-level back-end-of-line (BEOL) wiring structure, and further comprising:
forming third and fourth electrodes disposed in a second metallization level different than the first metallization level.
11. The method of claim 10 wherein the third electrode is directly connected with the first port, the fourth electrode is directly connected with the second port, and the third and fourth electrodes provide a fixed capacitance that is increased to provide the larger capacitance value when the first electrode is coupled by the first voltage-controlled unit with the first port and the second electrode is coupled by the second voltage-controlled unit with the second port.
12. The method of claim 10 wherein forming the third and fourth electrodes further comprises:
forming the third electrode with a lateral position in the second metallization level such that the third electrode is aligned vertically with the first electrode; and
forming the fourth electrode with a lateral position in the second metallization level such that the fourth electrode is aligned vertically with the second electrode.
13. The method of claim 12 further comprising:
forming a first plurality of metal-filled vias extending between the first electrode and the third electrode so that the first and third electrodes are shorted together; and
forming a second plurality of metal-filled vias extending between the second electrode and the fourth electrode so that the second and fourth electrodes are shorted together.
14. The on-chip capacitor of claim 1 wherein forming the first and second ports further comprises:
forming the first and second ports with a spaced-apart, substantially parallel arrangement.
15. The on-chip capacitor of claim 14 wherein forming the first and second electrodes further comprises:
forming the first and second electrodes between the first and second ports at an orientation that is approximately orthogonal relative to the first and second ports.
16. A method for tuning an on-chip capacitor during operation of an integrated circuit electrically coupled with the on-chip capacitor, the method comprising:
powering first and second ports of the on-chip capacitor with opposite polarities;
selectively connecting a first electrode with the first port using a first voltage signal supplied from the integrated circuit; and
selectively connecting a second electrode with the second port using a second voltage signal supplied from the integrated circuit.
17. The method of claim 16 wherein selectively connecting the first electrode with the first port further comprises:
operating a first voltage-controlled unit to generate the first voltage signal.
18. The method of claim 17 wherein selectively connecting the second electrode with the second port further comprises:
operating a second voltage-controlled unit to generate the second voltage signal.
19. The method of claim 18 where the first and second voltage-controlled units are operated concurrently by a single control bit effective to supply the first and second voltage signals.
20. The method of claim 16 further comprising:
continuously powering a plurality of electrodes directly connected with the first and second ports to supply a fixed capacitance so that the selective connection of the first and second electrodes adjusts the fixed capacitance.
21. A design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
an on-chip capacitor including first and second ports configured to be powered with opposite polarities, first and second electrodes, and first and second voltage-controlled units each configured to be switched between a first state in which the first and second electrodes are electrically isolated from the first and second ports and a second state, the first electrode electrically connected with the first port when the first voltage-controlled unit is switched to the second state and the second electrode electrically connected with the second port when the second voltage-controlled unit is switched to the second state,
wherein the on-chip capacitor has a larger capacitance value when the first and second voltage-controlled units are in the second state than when the first and second voltage-controlled units are in the first state.
22. The design structure of claim 21 wherein the design structure comprises a netlist.
23. The design structure of claim 21 wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.
24. The design structure of claim 21 wherein the design structure resides in a programmable gate array.