1. A frame rate conversion circuit comprising:
selection circuitry that receives a plurality of video signals and selects a video signal of the plurality of video signals;
a scaler positioning module that routes a first video signal path through a first scaler and a second video signal path through a second scaler, the scaler positioning module comprising:
a first scaler slot positioned within the first video signal path and configured to receive the selected video signal; and
a second scaler slot positioned within the second video signal path and configured to receive a video signal retrieved from storage, wherein the first scaler is coupled to the first scaler slot and the second scaler is coupled to the second scaler slot;
wherein the first scaler is configured to:
scale the selected video signal;
write the scaled selected video signal to a memory via a memory interface; and
output the scaled selected video signal to a first input of a selector; and
wherein the second scaler is configured to:
read the scaled selected video signal from the memory via the memory interface;
further scale the read scaled selected video signal; and
provide the further scaled selected video signal to a second input of the selector.
2. The frame rate conversion circuit of claim 1, wherein the second scaler is configured to output the read scaled selected video signal.
3. The frame rate conversion circuit of claim 1, wherein the scaler positioning module configures placement of a tearless control module in one of the first and second video signal paths.
4. The frame rate conversion circuit of claim 1, wherein the scaler positioning module outputs a scaled selected video signal to a blank time optimizer.
5. A scaler positioning module comprising:
three scaler positioning slots;
a first scaler; and
a second scaler, wherein the scaler positioning module is operative to selectively:
position a selected one of the first scaler and second scaler in a first scaler positioning slot, by routing a first signal path comprising the first scaler positioning slot through the selected scaler, to synchronously scale an input video signal;
position a selected one of the first scaler and second scaler in a second scaler positioning slot, by routing a second signal path comprising the second scaler positioning slot through the selected scaler, to down-scale the input video signal and write the down-scaled video signal to a memory; and
position a selected one of the first scaler and second scaler in a third scaler positioning slot, by routing a third signal path comprising the third scaler positioning slot through the selected scaler, to up-scale a video signal read from the memory.
6. The scaler positioning module of claim 5, wherein the scaler in the first scaler positioning slot locks the input video signal to an output video signal.
7. The scaler positioning module of claim 5, further comprising selection circuitry that receives scaled data from the scaler in at least one of the slots and selectively outputs the scaled data from the scaler positioning module.
8. The scaler positioning module of claim 7, further comprising a write FIFO buffer and a read FIFO buffer, wherein the scaler in a first one of the slots writes the scaled data to the memory via the write FIFO buffer and the scaler in a second one of the slots reads the scaled data from the memory via the read FIFO buffer.
9. The scaler positioning module of claim 8, wherein the selection circuitry receives the read scaled data from the read FIFO buffer and selectively outputs the read scaled data from the scaler positioning module output.
10. A method for performing frame rate conversion comprising:
receiving a plurality of video signals;
selecting a video signal of the plurality of video signals;
routing a first video signal path comprising a first scaler slot through a first scaler, wherein the first scaler slot is configured to receive the selected video signal;
routing a second video signal path comprising a second scaler slot through a second scaler, wherein the second scaler slot is configured to receive a video signal retrieved from storage; and
scaling the selected video signal, wherein the scaled first selected video signal is output to a blank time optimizer.
11. The method of claim 10, further comprising writing the scaled selected video signal to a memory via a memory interface.
12. The method of claim 11, further comprising providing the scaled selected video signal to a first input of a selector.
13. The method of claim 12, further comprising:
reading the scaled selected video signal from the memory via the memory interface;
further scaling the read scaled selected video signal; and
providing the further scaled selected video signal to a second input of the selector.
14. The method of claim 13, further comprising outputting the read scaled selected video signal.
15. The method of claim 11, further comprising configuring placement of a tearless control module within one of the first and second video signal paths.
16. The method of claim 10, further comprising selecting a second of the plurality of video signals, scaling the second selected video signal, and outputting the scaled second selected video signal.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A compound of formula 1 or a pharmaceutically acceptable salt or hydrate:
wherein:
X is N;
Y is O or S;
W is N;
R1, R2, and R3 each independently is hydrogen or halogen;
R4, R5, and R6 each independently is hydrogen, halogen, C1\u02dcC8 straight or branched alkyl, \u2014C1-C8 straight or branched alkoxy, nitro, cyano, \u2014COOR7, \u2014CH2\u2014O\u2014R8, \u2014CH2 COOR7, or \u2014COR7;
Each R7 independently is hydrogen or C1\u02dcC8 straight or branched alkyl; and
R8 is hydrogen or cyano.
2. The compound according to claim 1, having formula III:
wherein:
W is N;
R1, R2, and R3 each independently is hydrogen or halogen;
R4, R5, and R6 each independently is hydrogen, halogen, C1-C8 straight or branched alkyl, C1-C8 straight or branched alkoxy, nitro, cyano, \u2014COOR7, \u2014CH2\u2014O\u2014R8, \u2014CH2COOR7, or \u2014COR7;
each R7 independently is hydrogen or C1-C8 straight or branched alkyl; and
R8 is hydrogen or cyano.
3. The compound according to claim 1, wherein said compound is selected from the group consisting of:
6-{2-4-(3,6-dichloropyridazin-4-yl)piperazin-1-yl-ethoxy}-nicotinic acid ethyl ester, and
6-{2-4-(3,6-dichloropyridazin-4-yl)piperazin-1-yl-ethoxy}-nicotinic acid methyl ester.
4. A pharmaceutical composition, comprising at least one of the compounds of the formula I or a pharmaceutically acceptable salt according to claim 1 as well as one or more pharmaceutically acceptable carriers or excipients.