1. A sexual pleasure device comprising:
an elastomeric sleeve including an elongated cavity;
a rigid housing at least partially surrounding the elastomeric sleeve; and
a pressure element disposed proximal to an inner surface of the rigid housing and distal to and operably engaged with the elastomeric sleeve; and
an actuator disposed distal to the rigid housing and connected to the pressure element,
wherein the actuator is operable to control movements of the pressure element, relative to the housing, thereby to apply pressure to the elastomeric sleeve.
2. The sexual pleasure device of claim 1, wherein the elongated cavity is configured to simulate a vagina.
3. The sexual pleasure device of claim 1, wherein the rigid housing is approximately cylindrical.
4. The sexual pleasure device of claim 1, wherein the pressure element is disposed in a discrete region, and wherein the actuator is operable to displace the pressure element, thereby to impose a localized pressure on the elastomeric sleeve.
5. The sexual pleasure device of claim 1, wherein the actuator is operable to control movements of the pressure element, relative to the housing, thereby to adjust a volume of the elongated cavity.
6. The sexual pleasure device of claim 1, wherein the actuator is operable to affect a reduction in the volume of the elongated cavity only in a region proximate the pressure element.
7. The sexual pleasure device of claim 1, wherein the actuator is operable to affect a reduction in the volume of the elongated cavity localized to one side of the cavity.
8. The sexual pleasure device of claim 1, wherein displacement of the actuator, relative to the rigid housing, within a first region along a length of the elongated cavity effects a reduction in the volume of the elongated cavity in a second region, along the length of the elongated cavity.
9. The sexual pleasure device of claim 1, further comprising a pivot point about which the pressure element can move.
10. The sexual pleasure device of claim 1, wherein the pivot point is removable.
11. The sexual pleasure device of claim 1,
wherein the elastomeric sleeve includes an opening arranged to accommodate insertion of a male sex organ into the elongated cavity,
wherein the rigid housing comprises:
a first region, along a length of the rigid housing, arranged proximate to the opening; and
a second region, along the length of the rigid housing, associated with a majority of the length rigid housing, and
wherein a cross-sectional area of the first region is larger than a cross-sectional area of the second region.
12. The sexual pleasure device of claim 11, wherein the actuator defines a control surface, and wherein the control surface is disposed predominately within the second region along a length of the rigid housing.
13. The sexual pleasure device of claim 1, wherein the elastomeric sleeve comprises an elastomeric gel formed from a mixture of plasticizing oil and a block copolymer, the block copolymer comprising an admixture of (i) a styrene ethylene butylene styrene block copolymer and (ii) a styrene ethylene propylene styrene block copolymer combined in a ratio of approximately 1:4 to 4:1.
14. The sexual pleasure device of claim 1, wherein the rigid housing includes a grasping region arranged to be grasped by a user for manipulation of the device, and wherein the actuator is disposed within the grasping region.
15. The device of claim 1 wherein the actuator is a manually operable handle.
16. The device of claim 1 further including at least one stanchion disposed between the actuator and the pressure element.
17. The device of claim 16 further including a hole in the rigid housing through which passes said at least one stanchion.
18. The device of claim 1 wherein the pressure element may rotate relative to the housing.
19. A method for providing sexual pleasure, the method comprising: inserting a male sex organ into a cavity of an elastomeric sleeve, the elastomeric sleeve being at least partially surrounded by a rigid housing engaging an actuator disposed distal to the rigid housing and exposed to manual contact to effect movement of a pressure element disposed proximal to the rigid housing and distal to and operably engaged with the elastomeric sleeve, thereby modifying a sensation perceived by the male sex organ.
20. The method of claim 19, wherein engaging the actuator comprises applying a first force to the actuator, and wherein the first force is applied within a first region along a length of the cavity and a resulting increase in pressure is applied to the male sex organ within a second region, at a distance from the first region, along the length of the cavity.
21. The method of claim 19, further comprising dynamically controlling the sensation perceived by the male sex organ as a function of time.
22. The method of claim 21 wherein the dynamically controlled sensation is modified contemporaneously at the manual command of the user.
23. The method of claim 19, further comprising dynamically controlling the sensation perceived by the male sex organ selectively as a function of location along a length of the elastomeric sleeve.
24. The method of claim 23 wherein the dynamically controlled sensation is modified contemporaneously at the command of the user.
25. The method of claim 19, further comprising dynamically controlling the sensation perceived by the male sex organ as a function of force applied to the actuator.
26. The method of claim 25 wherein the dynamically controlled sensation is modified manually.
27. The method of claim 19, wherein modifying the sensation comprises increasing a pressure applied to the male sex organ via the elastomeric sleeve at a location proximal to the pressure element.
28. The method of claim 19, wherein a plurality of sensations may be provided in the absence of linear displacement between the sex organ and the cavity.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A semiconductor memory with static memory cells, comprising:
a first-conductivity-type well contained in the memory cells, configured to include second-conductivity-type transistors;
a second-conductivity-type well contained in the memory cell, configured to include first-conductivity-type transistors;
a first power source line configured to supply a first voltage;
a second power source line configured to supply a second voltage;
a third power source line configured to supply a third voltage; and
first switch coupled to the first and second power source lines, configured to provide the first-conductivity-type well with one of the first and second voltages in response to a switching signal.
2. The semiconductor memory as claimed in claim 1, wherein the first switch provides the first-conductivity-type well with the second voltage if the memory cell is in a standby state, and the first switch provides the first-conductivity-type well with the first voltage if the memory cell is in a selected state.
3. The semiconductor memory as claimed in claim 2, wherein the first-conductivity-type well is a p-type well, and the second-conductivity-type transistors are n-type transistors.
4. The semiconductor memory as claimed in claim 3, wherein the first voltage is higher than the second voltage.
5. The semiconductor memory as claimed in claim 2, wherein the first-conductivity-type well is an n-type well, and the second-conductivity-type transistors are p-type transistors.
6. The semiconductor memory as claimed in claim 5, wherein the first voltage is lower than the second voltage.
7. The semiconductor memory as claimed in claim 1, wherein the first switch supplies one of the first and second voltage to each memory cell block.
8. The semiconductor memory as claimed in claim 1, wherein the second-conductivity-type transistors are MIS (metal insulator semiconductor) transistors.
9. The semiconductor memory as claimed in claim 1, further comprising:
a fourth power source line configured to supply a fourth voltage; and
second switch coupled to the third and fourth power source lines, configured to provide the second-conductivity-type well with one of the third and fourth voltages in response to the switching signal.
10. The semiconductor memory as claimed in claim 9, wherein:
the first switch provides the first-conductivity-type well with the second voltage if the memory cell is in a standby state, and the first switch provides the first-conductivity-type well with the first voltage if the memory cell is in a selecting state; and
the second switch provides the second-conductivity-type well with the fourth voltage if the memory cell is in the standby state, and the second switch provides the second-conductivity-type well with the third voltage if the memory cell is in the selected state.
11. The semiconductor memory as claimed in claim 10, wherein the first-conductivity-type well is a p-type well, the second-conductivity-type transistors are n-type transistors, the second-conductivity-type well is an n-type well, and the first-conductivity-type transistors are p-type transistors.
12. The semiconductor memory as claimed in claim 11, wherein the first voltage is higher than the second voltage, and the third voltage is lower than the fourth voltage.
13. The semiconductor memory as claimed in claim 9, wherein:
the first switching means supplies one of the first and second voltages memory cell by memory cell; and
the second switching means supplies one of the third and fourth voltages memory cell to each memory cell block.
14. The semiconductor memory as claimed in claim 9, wherein the first-conductivity-type and second-conductivity-type transistors are MIS (metal insulator semiconductor) transistors.
15. The semiconductor memory as claimed in claim 1, wherein the switching signal is an SWL (section word line) signal.
16. The semiconductor memory as claimed in claim 1, wherein the first switch is formed in a non-memory cell area where a driver for driving a section word line is formed.
17. The semiconductor memory as claimed in claim 16, wherein the second power source line is formed in the non-memory cell area.
18. The semiconductor memory as claimed in claim 17, wherein the second power source line is substantially in parallel with bit lines.
19. A semiconductor memory with static memory cells, comprising:
a first-conductivity-type well contained in each of the memory cells and including second-conductivity-type transistors;
a second-conductivity-type well contained in the memory cell and including first-conductivity-type transistors;
a first power source line coupled to the first-conductivity-type well, configured to supply one of first and second voltages;
a second power source line configured to supply a third voltage; and
switching means coupled to the first power source line, configured to provide the first power source line with one of the first and second voltages in response to a switching signal.
20. The semiconductor memory as claimed in claim 19, wherein the first switch provides the first-conductivity-type well with the second voltage if the memory cell is in a standby state, and the first switch provides the first-conductivity-type well with the first voltage if the memory cell is in a selected state.
21. The semiconductor memory as claimed in claim 20, wherein the first-conductivity-type well is a p-type well, and the second-conductivity-type transistors are n-type transistors.
22. The semiconductor memory as claimed in claim 21, wherein the first voltage is higher than the second voltage.
23. The semiconductor memory as claimed in claim 20, wherein the first-conductivity-type well is an n-type well, and the second-conductivity-type transistors are p-type transistors.
24. The semiconductor memory as claimed in claim 23, wherein the first voltage is lower than the second voltage.
25. The semiconductor memory as claimed in claim 19, wherein the first switch supplies one of the first and second voltages to each memory cell block.
26. The semiconductor memory as claimed in claim 19, wherein the second-conductivity-type transistors are MIS (metal insulator semiconductor) transistors.
27. The semiconductor memory as claimed in claim 19, further comprising:
a fourth power source line configured to supply a fourth voltage; and
second switch coupled to the third and fourth power source lines, configured to provide the second-conductivity-type well with one of the third and fourth voltages in response to the switching signal.
28. The semiconductor memory as claimed in claim 27, wherein:
the first switch provides the first-conductivity-type well with the second voltage if the memory cell is in a standby state, and the first switch provides the first-conductivity-type well with the first voltage if the memory cell is in a selecting state; and
the second switch provides the second-conductivity-type well with the fourth voltage if the memory cell is in the standby state, and the second switch provides the second-conductivity-type well with the third voltage if the memory cell is in the selected state.
29. The semiconductor memory as claimed in claim 28, wherein the first-conductivity-type well is a p-type well, the second-conductivity-type transistors are n-type transistors, the second-conductivity-type well is an n-type well, and the first-conductivity-type transistors are p-type transistors.
30. The semiconductor memory as claimed in claim 29, wherein the first voltage is higher than the second voltage, and the third voltage is lower than the fourth voltage.
31. The semiconductor memory as claimed in claim 27, wherein:
the first switching means supplies one of the first and second voltages memory cell by memory cell; and
the second switching means supplies one of the third and fourth voltages memory cell by memory cell.
32. The semiconductor memory as claimed in claim 27, wherein the first-conductivity-type and second-conductivity-type transistors are MIS (metal insulator semiconductor) transistors.
33. The semiconductor memory as claimed in claim 19, wherein the switching signal is an SWL (section word line) signal.
34. The semiconductor memory as claimed in claim 19, wherein the switching means includes:
a level shifter containing:
an input terminal configured to receive the switching signal;
a first output terminal; and
a second output terminal,
wherein the level shifter provides one of the first and second output parts with an ON signal in response to the switching signal;
a first transistor circuit coupled to the first output part, for providing the first power source line with the first voltage in response to the ON signal; and
a second transistor circuit coupled to the second output part, for providing the first power source line with the second voltage in response to the ON signal.
35. The semiconductor memory as claimed in claim 19, wherein the first switch is formed in a non-memory cell area where a driver for driving a section word line is formed.
36. The semiconductor memory as claimed in claim 35, wherein the second power source line is formed in the non-memory cell area.
37. The semiconductor memory as claimed in claim 36, wherein the second power source line is substantially in parallel with bit lines.