1. A storage system, comprising:
a first mounting plate operatively coupled to a wheel;
a second mounting plate spaced from said first mounting plate and operatively coupled to a plurality of wheels;
at least one of said first and second mounting plates comprising a plurality arched channels, each channel configured to receive a fastener;
a first wheel assembly spaced from said first mounting plate;
a second wheel assembly spaced from said second mounting plate;
a cable operatively engaging each of said wheels operatively coupled to said first mounting plate or said second mounting plate;
a coupler extending from said first wheel assembly and a second coupler extending from said second wheel assembly; and
a self-locking mechanism coupled to said second mounting plate, said self-locking mechanism comprising a first bracket rotationally coupled to said second mounting plate and a second bracket directly coupled to said first bracket;
wherein said second bracket pivots at a point of said direct coupling;
wherein each of said mounting plates comprises a base portion configured to be mounted substantially parallel to a mounting surface.
2. A storage system according to claim 1, wherein each of said mounting plates comprises a plurality of sides extending downward from said base.
3. A storage system according to claim 2, wherein said base and said plurality of sides are a unitary structure.
4. A storage system according to claim 3, wherein said base and said plurality of sides are stamped sheet metal.
5. A storage system according to claim 1, wherein said coupler and said second coupler each comprise a strap operatively coupled to a carabineer.
6. A storage system, comprising:
a first plate and a second plate, each plate having a top with a base portion, a plurality of downwardly extending portions, and a plurality of fastener-receiving arched channels,
at least one pulley rotatably coupled to said plurality of downwardly extending portions for each of said plates;
a plurality of pulleys extending downward from said plates; and
a cable operatively engaging said pulleys coupled to said plates and said pulleys extending downward from said plates;
wherein said second plate has a second pulley rotatably coupled to said plurality of downwardly extending portions;
said storage system further comprising a self-locking mechanism coupled to said second plate, said self-locking mechanism comprising a first bracket coupled to said downwardly extending portions and a second bracket mounted to said first bracket at an open end of said second bracket;
wherein said second bracket pivots at a point or said mounting.
7. A storage system according to claim 6, wherein said downwardly extending portions are generally parallel.
8. A storage system according to claim 6, wherein each of said downwardly extending pulleys is coupled to a pulley frame, and each pulley frame engages a coupling mechanism.
9. A storage system, comprising:
two plates, each plate having a top with a base portion and a plurality of extensions extending away from said base portion and generally coplanar with said base portion;
said base portions comprising a plurality of fastener-receiving arched channels;
said plates further comprising a plurality of downwardly extending portions,
wherein each downwardly extending portion has top edges adjacent to at least two of said extensions;
at least one pulley rotatably coupled to said plurality of downwardly extending portions for each of said plates;
a plurality of pulleys extending downward from said plates; and
a cable operatively engaging said pulleys coupled to said plates and said pulleys extending downward from said plates
wherein a second plate has a second pulley rotatably coupled to said plurality of downwardly extending portions
said storage system further comprising a self-locking mechanism coupled to said second plate,
wherein said self-locking mechanism comprises a first bracket coupled to said downwardly extending portions and a second bracket coupled to said first bracket.
10. A storage system according to claim 9, wherein said edges of said downwardly extending portions are integral with edges of said extensions.
11. A storage system according to claim 9, wherein said downwardly extending portions are generally parallel.
12. A storage system according to claim 9, wherein each of said downwardly extending pulleys is coupled to a pulley frame, and each pulley frame engages a coupling mechanism.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A memory system comprising:
a primary memory controller;
a point-to-point memory data bus, having an effective bit-width m, coupled to the primary memory controller;
at least one memory module directly connected to the primary controller via a segment of the memory data bus, the memory module having a module data bus with an effective bit-width N=R\xd7m, where R is an integer value greater than one, the memory module comprising an interface circuit coupled between the memory data bus and the module data bus, the interface circuit capable of performing m-bit-wide data transfers on the memory data bus, the interface circuit capable of performing N-bit-wide data transfers on the module data bus, said interface circuit comprising:
R m-bit-wide data registers, each register capable of exchanging point-to-point data signaling with a corresponding rank of memory devices; and
a multiplexer, having a multiplexing ratio R, coupled between the R data registers and the memory data bus; and
one additional segment of the memory data bus for each additional memory module, the additional segment directly connecting the additional memory module to the module immediately preceding it.
2. The memory system of claim 1, wherein the memory data bus further comprising a ring data bus segment connecting the last of the memory modules in the memory system back to the primary memory controller.
3. The memory system of claim 1, wherein the memory data bus and the module data bus each having a clock rate, the memory data bus clocking at a rate R times the clock rate of the module data bus.
4. A memory module comprising:
R ranks of memory devices, where R is at least two, each rank having an m-bit-wide data port;
a module data port capable of exchanging data signaling over a memory data bus having an effective bit-width m;
an interface circuit coupled between the module data port and the R memory-device-rank data ports, the interface circuit capable of performing m-bit-wide data transfers at the module data port, the interface circuit capable of performing R\xd7m-bit-wide data transfers with the R ranks of memory devices, said interface circuit comprising:
R m-bit-wide data registers, each register capable of exchanging point-to-point data signaling with a corresponding rank of memory devices through the data port of that rank; and
a multiplexer, having a multiplexing ratio R, coupled between the R data registers and the external data port; and
a controller capable of synchronizing the operation of the interface circuit and the memory device ranks such that a data transfer comprising R serial data transfers on the memory data bus can be completed internal to the memory module with one R\xd7m-bit-wide data transfer with the memory device ranks.
5. The memory module of claim 4, wherein the controller supplies rank selection signals to the multiplexer and register latching signals to each of the data registers.
6. The memory module of claim 4, wherein data signaling between a data register and its rank of memory devices further comprises a bit mask received from the memory data bus along with a corresponding m bits, the multiplexer transferring the bit mask to the data register along with the corresponding m bits.
7. The memory module of claim 4, wherein the controller is capable of synchronizing the operation of the data registers, the module data port, and the multiplexerdemultiplexer in order to serialize data from a subset of the data registers onto the memory data bus.
8. The memory module of claim 4, wherein data transfers between one of the data registers and the corresponding rank of memory devices occurs at a clock rate related to the clock rate of the memory data bus by a factor 1R.
9. The memory module of claim 4, where the module is a dual-inline memory module comprising a printed circuit board capable of connection to the memory data bus via insertion of the circuit board into a card edge connector connected to the memory data bus.
10. The memory module of claim 9, wherein R equals two, one of the two ranks of memory devices arranged on each side of the circuit board and connected to the corresponding data register via a set of module data signaling lines routed on the circuit board.
11. The memory module of claim 9, where the interface circuit comprises two interface circuits each serving half of the module data port and half of each rank of memory devices.
12. The memory module of claim 4, wherein the module data port comprises a dual-port buffer, each port of the dual-port buffer capable of connection to another memory module in a point-to-point configuration of memory data bus segments.
13. The memory module of claim 12, wherein each port is capable of connection to an m-bit-wide memory data bus segment, wherein one port comprises a transfer port and the other port comprises a forwarding port, the module capable of using the transfer port to transfer data signals between the interface circuit and a higher-level controller connected to the memory data bus, the module capable of using the forwarding port to connect to a second memory module in order to transfer data signals between the transfer port on the first memory module and the transfer port on the second memory module.
14. The memory module of claim 12, wherein each module data port is capable of connection to an m2-bit-wide memory data bus segment, wherein the dual module data ports comprise first and second transferforwarding ports, the module capable of retransmitting data signals received at one of the transferforwarding ports, but not destined for that memory module, on the other transferforwarding port, the module also capable of transferring m2 data signals between each of the transferforwarding ports and the interface circuit.
15. The memory module of claim 4, wherein data exchanges over the memory data bus comprise a data strobe signal, the module further comprising a data strobe circuit to generate data strobe signaling when transmitting data over the memory data bus.
16. The memory module of claim 15, wherein the controller begins an internal sequence of interface circuit write operations in response to an externally-supplied data strobe signal.
17. The memory module of claim 4, wherein data exchanges between the interface circuit and the ranks of memory devices comprise a data strobe signal, the module further comprising a data strobe circuit to generate data strobe signaling when transmitting data from the interface circuit to the ranks of memory devices, the interface circuit comprising a register circuit to latch data from the ranks of memory devices based on data strobe signaling received from those devices.
18. A method of hostmemory communication comprising:
initiating a data access transaction, involving N data bits, between a memory controller and a memory module;
at the memory module, initiating a corresponding data access transaction between an interface circuit and R ranks of memory devices, each rank capable of m-bit-wide data transfers, R>1;
transferring the N data bits between the memory controller and the memory module in m-bit-wide data segments;
transferring the N data bits between the interface circuit and the R ranks of memory devices in M R\xd7m-bit-wide segments, where
M
=
N
R
\xd7
m
is an integer value; and
initiating a valid data access transaction when N is an integer multiple of m, but less than R\xd7m.
19. The method of claim 18, wherein N=R\xd7m, such that for R data segments transferred between the memory controller and the memory module, one transfer occurs between the interface circuit and the memory devices.
20. The method of claim 18, further comprising clocking transfers between the memory controller and the memory module at R times the rate that transfers are clocked between the interface circuit and the memory devices.
21. The method of claim 18, wherein when the data access transaction is a write transaction, transferring the N data bits between the interface circuit and Nm of the ranks of memory devices, while signaling the remainder of the ranks to ignore the write transaction.
22. The method of claim 18, wherein when the data access transaction is a read transaction, transferring R\xd7m data bits, including the N data bits requested for the read transaction, from the R ranks of memory devices to the interface circuit, and transferring the N data bits requested for the read transaction from the memory module to the memory controller.
23. A memory module comprising:
R ranks of memory devices, where R is at least two, each rank having an m-bit-wide data port;
a module data port capable of exchanging data signaling over a memory data bus having an effective bit-width m, the module data port comprising a dual-port buffer, each port of the dual-port buffer capable of connection to another memory module in a point-to-point configuration of memory data bus segments, each port capable of connection to an m-bit-wide memory data bus segment, wherein one port comprises a transfer port and the other port comprises a forwarding port, the module capable of using the transfer port to transfer data signals between the interface circuit and a higher-level controller connected to the memory data bus, the module also capable of using the forwarding port to connect to a second memory module in order to transfer data signals between the transfer port on the first memory module and the transfer port on the second memory module;
an interface circuit coupled between the module data port and the R memory-device-rank data ports, the interface circuit capable of performing m-bit-wide data transfers at the module data port, the interface circuit capable of performing R\xd7m-bit-wide data transfers with die R ranks of memory devices; and
a controller capable of synchronizing the operation of the interface circuit and the memory device ranks such that a data transfer comprising R serial data transfers on the memory data bus can be completed internal to the memory module with one R\xd7m-bit-wide data transfer with the memory device ranks.
24. A memory module comprising:
R ranks of memory devices, where R is at least two, each rank having an m-bit-wide data port;
a module data port capable of exchanging data signaling over a memory data bus having an effective bit-width m, the module data port comprising a dual-port buffer, each port of the dual-port buffer capable of connection to another memory module in a point-to-point configuration of memory data bus segments, each module data port capable of connection to an m2-bit-wide memory data bus segment, wherein the dual module data ports comprise first and second transferforwarding ports, the module capable of retransmitting data signals received at one of the transferforwarding ports, but not destined for that memory module, on the other transferforwarding port, the module also capable of transferring m2 data signals between each, of the transferforwarding ports and the interface circuit;
an interface circuit coupled between the module data port and the R memory-device-rank data ports, the interface circuit capable of performing m-bit-wide data transfers at the module data port, the interface circuit capable of performing R\xd7m-bit-wide data transfers with the R ranks of memory devices; and
a controller capable of synchronizing the operation of the interface circuit and the memory device ranks such that a data transfer comprising R serial data transfers on the memory data bus can be completed internal to the memory module with one R\xd7m-bit-wide data transfer with the memory device ranks.