1. A driving apparatus having a discharge tube lamp, comprising:
a DC power supplier for producing DC power;
a burst mode inverter for converting the DC power to AC power, wherein the inverter responds to a Pulse Width Modulation frequency to modulate the DC power to produce the AC power, wherein the AC power is pulse width modulated; and
a controller for generating the Pulse Width Modulation frequency and adjusting a duty-on-time of the Pulse Width Modulation frequency in the range of about 40% to 99%,
wherein the controller multiplies a frame frequency to generate the Pulse Width Modulation frequency, and wherein the controller adjusts the duty-on time of the Pulse Width Modulation frequency to be within 40% and 99% of one period of the Pulse Width Modulation frequency.
2. The driving apparatus according to claim 1, further comprising at least one discharge tube for being driven by AC power supplied from the inverter.
3. The driving apparatus according to claim 1, wherein the controller receives the frame frequency and adjusts the Pulse Width Modulation frequency to be between 2 and 3 times the frame frequency.
4. The driving apparatus according to claim 1, wherein the duty-on-time of the Pulse Width Modulation frequency is 40% and the Pulse Width Modulation frequency is three times the frame frequency.
5. The driving apparatus according to claim 1, wherein the duty-on-time of the Pulse Width Modulation frequency is in the range of 50% to 99% and the Pulse Width Modulation frequency is twice the frame frequency.
6. A driving method of a discharge tube lamp, comprising:
producing DC power;
generating a Pulse Width Modulation frequency and adjusting a duty-on-time of the Pulse Width Modulation frequency in the range of about 40% to 99%; and
utilizing the Pulse Width Modulation frequency to convert the DC power into AC power to be applied to the discharge tube lamp, wherein the AC power is pulse width modulated;
wherein generating the Pulse Width Modulation frequency includes multiplying a frame frequency to generate the Pulse Width Modulation frequency, and adjusting the duty-on time of the Pulse Width Modulation frequency to be within 40% and 99% of one period of the Pulse Width Modulation frequency.
7. The driving method according to claim 6, wherein adjusting the generated Pulse Width Modulation frequency includes adjusting the Pulse Width Modulation frequency to be 2 to 3 times the frame frequency in response to the signal.
8. The driving method according to claim 7, wherein the duty-on-time is in the range of 50% to 99% and the Pulse Width Modulation frequency is twice the frame frequency.
9. The driving method according to claim 7, wherein the duty-on-time of the Pulse Width Modulation frequency is 40% and the Pulse Width Modulation frequency is three times the frame frequency.
10. A liquid crystal display, comprising:
a liquid crystal display panel;
a DC power supplier for producing DC power;
a burst mode inverter for converting the DC power to AC power, wherein the inverter responds to a Pulse Width Modulation frequency to modulate the DC power to produce the AC power, wherein the AC power is pulse width modulated;
a controller for generating the Pulse Width Modulation frequency and adjusting a duty-on-time of the Pulse Width Modulation frequency in the range of about 40% to 99%; and
at least one discharge tube which turns on in accordance with the AC power supplied from the inverter to irradiate light to the liquid crystal display panel,
wherein the controller multiplies a frame frequency to generate the Pulse Width Modulation frequency, and wherein the controller adjusts the duty-on time of the Pulse Width Modulation frequency to be within 40% and 99% of one period of the Pulse Width Modulation frequency.
11. The liquid crystal display according to claim 10, wherein controller receives the signal having the frame frequency, and wherein the Pulse Width Modulation frequency is adjusted to be within the range of 2 to 3 times the frame frequency.
12. The liquid crystal display according to claim 10, wherein the duty-on-time of the Pulse Width Modulation frequency is 40% and the Pulse Width Modulation frequency is three times the frame frequency.
13. The liquid crystal display according to claim 10, wherein the duty-on-time of the Pulse Width Modulation frequency is in the range of 50% to 99% and the Pulse Width Modulation frequency is twice the frame frequency.
14. The driving apparatus according to claim 1, wherein the adjusted Pulse Width Modulation frequency is about 2.5 times the frame frequency.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method, comprising:
enabling a plurality of network processors to access a first shared memory store and a second shared memory store; and
employing a portion of the first shared memory store as a memory cache for the second shared memory store;
each network processor having a cache management component retrieving data from the memory cache, and a content addressable memory component performing content based searches of the first and second shared memory stores.
2. The method of claim 1, wherein the first shared memory store and the second shared memory store are selected from a group of shared memory stores consisting of dynamic random access memory (DRAM), Rambus dynamic random access memory (RDRAM), static random access memory (SRAM), reduced latency dynamic random access memory (RLDRAM), double data rate dynamic random access memory (DDR DRAM), double data rate two dynamic random access memory (DDR-2), double data rate three dynamic random access memory (DDR-3), and fast cycle dynamic random access memory (FCDRAM).
3. The method of claim 1, further comprising:
configuring the memory cache as a cache array including a plurality of cache lines; and
maintaining a local address-to-cache line map in the cache management component of each network processor in which cache lines associated with the respective network processor are mapped to corresponding memory addresses in an address space for the second shared memory store.
4. The method of claim 3, further comprising:
broadcasting a cache line access request to the plurality of network processors in response to a memory access request from a requesting network processor; and
performing a cache line lookup in the local address-to-cache line map of each network processor to determine which, if any, network processors own a cache line of the plurality of cache lines corresponding to the memory access request.
5. The method of claim 4, further comprising:
accessing the cache line to service the memory access request if it is determined that one of the network processors own the cache line; and
releasing ownership of the cache line by updating the local address-to-cache line map for the network processor that owned the cache line and assigning ownership of the cache line by updating the local address-to-cache line map for the requesting network processor.
6. The method of claim 4, further comprising:
retrieving data from the second shared memory store if it is determined that none of the network processors own the cache line;
selecting a cache line in the memory cache to replace;
copying data from the second shared memory store into the cache line selected for replacement; and
updating the local address-to-cache line map of the requesting network processor to assign ownership of the replaced cache line to the requesting network processor.
7. A computing apparatus comprising:
an internal interconnect;
a first memory store, coupled with the internal interconnect via a first memory controller;
a second memory store, coupled with the internal interconnect via a second memory controller;
a cache management component coupled with the internal interconnect to effectuate a memory cache in a portion of the first memory store corresponding to data in the second memory store; and
a content addressable memory component to perform content based searching of the first and second memory stores.
8. The computing apparatus of claim 7 wherein the first and second memory stores are selected from a group of memory stores consisting of dynamic random access memory (DRAM), Rambus dynamic random access memory (RDRAM), static random access memory (SRAM), reduced latency dynamic random access memory (RLDRAM), double data rate dynamic random access memory (DDR DRAM), double data rate two dynamic random access memory (DDR-2), double data rate three dynamic random access memory (DDR-3), and fast cycle dynamic random access memory (FCDRAM).
9. The computing apparatus of claim 7, wherein the first memory store comprises a static random access memory store and the second memory store comprises a Rambus dynamic random access memory store.
10. The computing apparatus of claim 7, wherein the content addressable memory component is implemented in software or firmware.
11. The computing apparatus of claim 7, wherein the content addressable memory component is implemented in hardware.
12. The computing apparatus of claim 7, wherein the content addressable memory component is integrated with the cache management component in hardware.
13. The computing apparatus of claim 7, wherein first memory store comprises a static random access memory store integrated onto the network processor.
14. The computing apparatus of claim 7, wherein the first memory store further comprises:
a plurality of non-contiguous memory cache regions; and
a plurality of non-contiguous general use regions.
15. The computing apparatus of claim 7, wherein the cache management component is configured to maintain a hardware-based cache tag array.
16. The computing apparatus of claim 7, wherein the cache management component further comprises:
a first computer instruction to support concurrent execution of a plurality of threads;
a second computer instruction to maintain an address tag array for each of said plurality of threads; and
a third computer instruction to maintain a data cache for each of said plurality of threads.
17. The computing apparatus of claim 7, wherein the cache management component, the internal interconnect, and the content addressable memory component comprise a network processor.
18. The computing apparatus of claim 17, further comprising:
a third memory store, coupled with the internal interconnect via an interface controller, wherein the interface controller is configured to receive memory access requests.
19. The computing apparatus of claim 18, wherein the interface controller comprises a front side bus interface controller integrated on the network processor.
20. The computing apparatus of claim 19, wherein the network processor further comprises a general-purpose processor component configured to store data on the second memory store.
21. The computing apparatus of claim 7, further comprising:
a fourth interface coupled between the first memory controller and the cache management component to transmit memory access requests.
22. A network processor, comprising:
an internal interconnect;
a first memory controller coupled with the internal interconnect to access a first off-chip memory store;
a second memory controller coupled with the internal interconnect to access a second off-chip memory store;
a first portion of the first off-chip memory store configured as a memory cache for the second off-chip memory store;
a cache management component coupled with the internal interconnect to retrieve data in the memory cache;
a content addressable memory component to perform content based searching of the first and second off-chip memory stores; and
a front side bus controller coupled with the internal interconnect to receive memory requests.
23. The network processor of claim 22, wherein the first off-chip memory store comprises static random access memory (SRAM).
24. The network processor of claim 22, wherein the second off-chip memory store is selected from a group of memory stores consisting of dynamic random access memory (DRAM), Rambus dynamic random access memory (RDRAM), static random access memory (SRAM), reduced latency dynamic random access memory (RLDRAM), double data rate dynamic random access memory (DDR DRAM), double data rate two dynamic random access memory (DDR-2), double data rate three dynamic random access memory (DDR-3), and fast cycle dynamic random access memory (FCDRAM).
25. The network processor of claim 22, further comprising:
a third memory controller coupled with the internal interconnect to access a third off-chip memory store, wherein the cache management component is configured to manage the memory cache corresponding to a memory address space for the third memory store.
26. The network processor of claim 25, wherein the third off-chip memory store is accessed via an off-chip front side bus and the off-chip front side bus is coupled with the front side bus controller.
27. The network processor of claim 25, wherein the third off-chip memory store is selected from a group of memory stores consisting of dynamic random access memory (DRAM), Rambus dynamic random access memory (RDRAM), static random access memory (SRAM), reduced latency dynamic random access memory (RLDRAM), double data rate dynamic random access memory (DDR DRAM), double data rate two dynamic random access memory (DDR-2), double data rate three dynamic random access memory (DDR-3), and fast cycle dynamic random access memory (FCDRAM).
28. The network processor of claim 22, further comprising:
a communication channel linking the first memory controller to the cache management component to transmit memory access requests.
29. The network processor of claim 22, wherein the cache management component is configured to maintain a hardware-based cache tag array.
30. The network processor of claim 22, wherein the cache management component is configured to manage a cache tag array in a second portion of the first off-chip memory store.
31. A system, comprising:
a first memory store, with a first interface;
a second memory store with a second interface; and
a network processor comprising:
an internal interconnect;
a first memory controller coupled with the internal interconnect to access the first memory store;
a second memory controller coupled with the internal interconnect to access the second memory store;
a cache management component coupled with the internal interconnect to effectuate a memory cache in a portion of the first memory store corresponding to data in the second memory store;
a content addressable memory component to perform content based searching of the first and second memory stores; and
an interface controller coupled with the internal interconnect to receive memory requests via the second interface.
32. The system of claim 31, wherein the first and second memory stores are selected from a group of memory stores consisting of dynamic random access memory (DRAM), Rambus dynamic random access memory (RDRAM), static random access memory (SRAM), reduced latency dynamic random access memory (RLDRAM), double data rate dynamic random access memory (DDR DRAM), double data rate two dynamic random access memory (DDR-2), double data rate three dynamic random access memory (DDR-3), and fast cycle dynamic random access memory (FCDRAM).
33. The system of claim 31, further comprising:
a third memory store coupled with a third interface, wherein the network processor further comprises an interface controller, coupled with the internal interconnect and further coupled with the third memory store via the third interface.
34. The system of claim 33, wherein the third memory store is selected from a group of memory stores consisting of dynamic random access memory (DRAM), Rambus dynamic random access memory (RDRAM), static random access memory (SRAM), reduced latency dynamic random access memory (RLDRAM), double data rate dynamic random access memory (DDR DRAM), double data rate two dynamic random access memory (DDR-2), double data rate three dynamic random access memory (DDR-3), and fast cycle dynamic random access memory (FCDRAM).
35. The system of claim 33, wherein the third interface comprises a front side bus interface, and the interface controller comprises a front side bus controller, wherein the cache management component and the front side bus controller are integrated.
36. The system of claim 31, wherein the cache management component is configured to maintain a hardware-based cache tag array.