1. A hooks module stored in a tangible computer readable medium and for use in a computer graphics system comprising graphics hardware controlled by a graphics library responsive to function calls generated by an executing graphics application, wherein the hooks module is configured to install at least one event generator in the graphics library during, and without interruption to, normal operations of the graphics application.
2. The hooks module of claim 1, wherein each of the at least one event generator is configured to perform a diagnostic operation during normal operations of the graphics application.
3. The hooks module of claim 2, wherein the graphics library comprises an applications program interface (API) for invoking the graphics library functions in response to commands generated by the graphics application, and wherein the at least one event generator comprises:
at least one API event generator operatively located in the graphics library API, each configured to perform selected diagnostic operations related to an associated one or more graphics library functions.
4. The hooks module of claim 2, wherein the at least one generator comprises:
at least one internal event generator adapted to be embedded in the graphics diagnostic library to perform selected diagnostic operations in response to a request by a graphics tool.
5. The hooks module of claim 4, wherein the graphics library further includes graphics hardware control modules for controlling the graphics hardware, and
wherein at least one of the at least one internal event generator is embedded in the graphics hardware control modules to provide the graphics diagnostic tool access to an associated operation in the graphics hardware control modules.
6. The hooks module of claim 4, wherein the graphics library includes pipeline control modules for managing a graphics pipeline in the graphics system,
wherein the at least one internal event generator comprise at least one pipeline control module event generator embedded in the pipeline control modules for providing the graphics diagnostic tool access to the pipeline control modules.
7. The hooks module of claim 4, wherein the graphics library includes device-specific control modules each configured to manage a specific portion of the graphics hardware, wherein the at least one internal event generator comprises:
at least one device-specific event generator configured to provide the linked graphics diagnostic tool access to the device-specific control modules.
8. The hooks module of claim 1, wherein the hooks module further comprises:
a normal operations dispatch table including function pointers to the graphics library functions;
a hooks dispatch table including function pointers to the at least one API event generator; and
a dispatch table manager constructed and arranged to copy selected portions of the normal operations dispatch table and the hooks dispatch table to an active dispatch table in the graphics library, wherein, in response to graphics application function calls, the API calls one of either the at least one API event generator or the graphics library functions in accordance with a function pointer located in the active dispatch table.
9. The hooks module of claim 1, wherein a graphics diagnostic tool and the hooks module communicate with each other through a interprocess communications (IPC) mechanisms providing socket communications between the graphics diagnostic tool and the hooks module.
10. The hooks module of claim 1, wherein the hooks module comprises at least one first event generator that causes the graphics system to incur significant performance penalties while performing diagnostic operations, and at least one second event generator that does not cause the graphics system to incur significant performance penalties while performing the diagnostic operations,
wherein the hooks module dynamically enables the at least one first event generator to temporarily perform the diagnostic operations only when required, and to permanently enable the at least one second event generator to perform the diagnostic operations continually.
11. A method for providing a graphics diagnostic tool access to a computer graphics system having graphics hardware and a graphics library for controlling the graphics hardware in response to function calls received from a graphics application executing thereon, the method comprising:
installing an event generator in the graphics library while the graphics application is executing, wherein the event generator is thereafter responsive to a graphics application function call.
12. The method of claim 11, wherein installing the event generator comprises:
receiving a graphics library function call issued by the graphics application to invoke a graphics library function;
invoking the event generator associated with that graphics library function;
performing diagnostic operations by the event generator; and
calling the associated graphics library function identified in the function call.
13. The method of claim 12, wherein invoking the event generator comprises:
forwarding results of the selected operations to the graphics tool.
14. The method of claim 12, wherein invoking the event generator comprises:
receiving a request from the graphics tool to perform the diagnostic operation;
installing an active dispatch table in the graphics library wherein the active dispatch table include only function pointers to those API event generators that perform diagnostic operations that will provide results requested by the graphics tool; and
calling one of either the API event generators or the graphics library function in response to a graphics library function call.
15. The method of claim 14, wherein installing an active dispatch table comprises:
providing a normal operations dispatch table having function pointers to the graphics library functions;
providing a hooks dispatch table including function pointers to the API event generators; and
copying selected portions of the normal operations dispatch table and the hooks dispatch table to the graphics library to form the active dispatch table in the graphics library.
16. The method of claim 11, wherein the graphics library is an OpenGL graphics library.
17. The method of claim 11, further comprising:
embedding in the graphics library an internal event generator; and
enabling the internal event generators in the graphics library in response to a request from the graphics tool; and
performing, by the internal event generator in response to the graphics tool, selected diagnostic operations, wherein the results provided to the graphics tool includes information pertaining to the graphics system.
18. The method of claim 11, wherein installing the event generator further comprises:
determining whether to install an entry point event generator in the graphics library during execution of the graphics application and without interrupting the execution of the graphics application.
19. A computer graphics system comprising:
a graphics library including graphics library functions responsive to function calls generated by a graphics application;
a hooks module integrated within a computer graphics system for dynamically linking a graphics diagnostic tool to at least one selected portion of the computer graphics system by inserting or removing a software program to or from the executing hooks module while the graphics application is executing on the graphics system, and without interrupting the execution of the graphics application.
20. The computer graphics system of claim 19, wherein the hooks module comprises:
a plurality of internal event generators embedded in the graphics library of the computer graphics system, each said event generator constructed and arranged to perform diagnostic operations during normal operations of the graphics application in response to requests generated by the graphics diagnostic tool.
21. The computer graphics system of claim 19, wherein the hooks module comprises at least one internal event generator that provides the graphics tool with access to internal state and control flow of the graphics system, and wherein the at least one internal event generators generate a stream of state information sufficient to recreate a current state of the graphics system.
22. A system for providing a graphics diagnostic tool access to a computer graphics system comprising graphics hardware and a graphics library for controlling the graphics hardware, the graphics library including graphics library functions responsive to function calls generated by an executing graphics application, the system comprising:
a plurality of internal event generators installed in the graphics library to perform diagnostic operations on the computer graphics system during normal operations of the graphics application.
23. The system of claim 22, wherein at least one of the diagnostic operations performed by the plurality of internal event generators provides the graphics tool with information pertaining to internal state and control flow of the computer graphics system.
24. The system of claim 22, wherein the graphics library further comprises at least one graphics hardware control module for controlling the graphics hardware, and wherein at least one of the plurality of internal event generators is embedded in one or more of the at least one control module to provide the graphics diagnostic tool access to an associated operation in the one or more control modules when the graphics diagnostic tool is attached to the computer graphics system.
25. The system of claim 22, wherein the graphics library comprises at least one pipeline control module for managing at least a portion of a graphics pipeline of the graphics system, and wherein the plurality of internal event generators comprise:
at least one pipeline control module event generator each embedded in a pipeline control module for providing the graphics diagnostic tool access to that pipeline control module when the graphics diagnostic tool is attached to the computer graphics system.
26. The system of claim 22, wherein the graphics library comprises at least one device-specific control module for managing at least a portion of the graphics hardware, and wherein the plurality of internal event generators comprises:
at least one device-specific event generator each providing the graphics tool access to one of the at least one device-specific control module when the graphics diagnostic tool is attached to the computer graphics system.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An intra-chip communication link comprising:
a transmit circuit operative to serialize a plurality of parallel inputs into at least one serial output,
a receive circuit operative to deserialize at least one serial input into a plurality of parallel outputs,
at least one first wire bond pad conductively coupled to said serial output,
at least one second wire bond pad conductively coupled to said serial input, and
at least one coaxial interconnect comprising a central conductor surrounded by a conductive outer shield and an insulator disposed therebetween,
wherein a first end of said central conductor is conductively coupled to said first wire bond pad and a second end of said central conductor is conductively coupled to said second wire bond pad.
2. The intra-chip communication link of claim 1 further comprising:
for at least one of each said plurality of parallel inputs a first circuit operatively coupled thereto, said first circuit comprising combinational and sequential elements, said sequential elements responding to assertion of a first system clock signal,
a first serial clock signal, each assertion of said first serial clock signal operative to conductively couple one of said plurality of parallel inputs to said serial output,
a second serial clock signal, each assertion of said second serial clock signal operative to conductively couple said serial input to at least one of said plurality of parallel outputs, and
for at least one of each said plurality of parallel outputs a second circuit operatively coupled thereto, said second circuit comprising combinational and sequential elements, said sequential elements responding to assertion of a second system clock signal,
wherein the propagation delay of said circuit elements of said first circuit is directly proportional to the duration of time between the assertion of said first system clock signal and the assertion of said first serial clock signal that conductively couples said parallel input to said serial output, and
wherein the propagation delay of said circuit elements of said second circuit is directly proportional to the duration of time between the assertion of said second serial clock signal that conductively couples said serial input to said parallel output and the assertion of said second system clock signal.
3. An intra-chip communication link comprising:
a transmit circuit operative to serialize a plurality of parallel inputs into at least one serial output,
a receive circuit operative to deserialize at least one serial input into a plurality of parallel outputs,
at least one first wire bond pad conductively coupled to said serial output,
at least one second wire bond pad conductively coupled to said serial input, and
at least one wafer-level package interconnect,
wherein a first end of said wafer-level package interconnect is conductively coupled to said first wire bond pad and a second end of said wafer-level package interconnect is conductively coupled to said second wire bond pad.
4. The intra-chip communication link of claim 3 further comprising:
for at least one of each said plurality of parallel inputs a first circuit operatively coupled thereto, said first circuit comprising combinational and sequential elements, said sequential elements responding to assertion of a first system clock signal,
a first serial clock signal, each assertion of said first serial clock signal operative to conductively couple one of said plurality of parallel inputs to said serial output,
a second serial clock signal, each assertion of said second serial clock signal operative to conductively couple said serial input to at least one of said plurality of parallel outputs, and
for at least one of each said plurality of parallel outputs a second circuit operatively coupled thereto, said second circuit comprising combinational and sequential elements, said sequential elements responding to assertion of a second system clock signal,
wherein the propagation delay of said circuit elements of said first circuit is directly proportional to the duration of time between the assertion of said first system clock signal and the assertion of said first serial clock signal that conductively couples said parallel input to said serial output, and
wherein the propagation delay of said circuit elements of said second circuit is directly proportional to the duration of time between the assertion of said second serial clock signal that conductively couples said serial input to said parallel output and the assertion of said second system clock signal.
5. An intra-chip communication link comprising:
a transmit circuit operative to serialize a plurality of parallel inputs into at least one serial output,
a receive circuit operative to deserialize at least one serial input into a plurality of parallel outputs,
at least one first wire bond pad conductively coupled to said serial output,
at least one second wire bond pad conductively coupled to said serial input, and
at least one coaxial interconnect comprising a central conductor surrounded by a conductive outer shield and an insulator disposed therebetween,
wherein a first end of said central conductor is conductively coupled to said first wire bond pad and a second end of said central conductor is conductively coupled to said second wire bond pad,
said intra-chip communication link further comprising:
for at least one of each said plurality of parallel inputs, a first circuit operatively coupled thereto, said first circuit comprising combinational and sequential elements, said sequential elements responding to assertion of a first system clock signal,
a first serial clock signal, each assertion of said first serial clock signal operative to conductively couple one of said plurality of parallel inputs to said serial output,
a second serial clock signal, each assertion of said second serial clock signal operative to conductively couple said serial input to at least one of said plurality of parallel outputs, and
for at least one of each said plurality of parallel outputs, a second circuit operatively coupled thereto, said second circuit comprising combinational and sequential elements, said sequential elements responding to assertion of a second system clock signal,
wherein the propagation delay of said circuit elements of said first circuit is directly proportional to the duration of time between the assertion of said first system clock signal and the assertion of said first serial clock signal that conductively couples said parallel input to said serial output, and
wherein the propagation delay of said circuit elements of said second circuit is directly proportional to the duration of time between the assertion of said second serial clock signal that conductively couples said serial input to said parallel output and the assertion of said second system clock signal.
6. An intra-chip communication link comprising:
a transmit circuit operative to serialize a plurality of parallel inputs into at least one serial output,
a receive circuit operative to deserialize at least one serial input into a plurality of parallel outputs,
at least one first wire bond pad conductively coupled to said serial output,
at least one second wire bond pad conductively coupled to said serial input, and
at least one wafer-level package interconnect,
wherein a first end of said wafer-level package interconnect is conductively coupled to said first wire bond pad and a second end of said wafer-level package interconnect is conductively coupled to said second wire bond pad,
said intra-chip communication link further comprising:
for at least one of each said plurality of parallel inputs, a first circuit operatively coupled thereto, said first circuit comprising combinational and sequential elements, said sequential elements responding to assertion of a first system clock signal,
a first serial clock signal, each assertion of said first serial clock signal operative to conductively couple one of said plurality of parallel inputs to said serial output,
a second serial clock signal, each assertion of said second serial clock signal operative to conductively couple said serial input to at least one of said plurality of parallel outputs, and
for at least one of each said plurality of parallel outputs, a second circuit operatively coupled thereto, said second circuit comprising combinational and sequential elements, said sequential elements responding to assertion of a second system clock signal,
wherein the propagation delay of said circuit elements of said first circuit is directly proportional to the duration of time between the assertion of said first system clock signal and the assertion of said first serial clock signal that conductively couples said parallel input to said serial output, and
wherein the propagation delay of said circuit elements of said second circuit is directly proportional to the duration of time between the assertion of said second serial clock signal that conductively couples said serial input to said parallel output and the assertion of said second system clock signal.