What is claimed is:
1. A method of operating a digital system having a cache with a plurality of lines, wherein each line has a plurality of segments, the method comprising the steps of:
determining a first miss in response to receiving a first request for a first segment in a first line of the cache;
fetching the first segment of a first plurality of segments in response to the first miss on the first line of the plurality of lines;
prefetching other segments of the first plurality of segments for the first line;
determining a second miss in response to receiving a second request for a second segment in a second line of the cache prior to completing the step of prefetching other segments of the first plurality of segments; and
halting the step of prefetching other segments of the first plurality of segments in response to the second miss and fetching the second segment of a second plurality of segments in response to the second miss.
2. The method according to claim 1, wherein the step of prefetching is cancelled in response to the second miss.
3. The method of claim 1, further comprising the step of prefetching other segments of the second plurality of segments while the step of prefetching other segments of the first plurality of segments is halted.
4. The method according to claim 3, further comprising the step of resuming prefetching other segments of the first plurality of segments after completing the step of prefetching other segments of the second plurality of segments.
5. The method according to claim 1, further comprising the steps of:
assigning a first priority to the first miss and a second priority to the second miss;
determining if the second priority is less important than the first priority; and
wherein the step of halting is not performed if the second priority is less important than the first priority.
6. The method according to claim 1, wherein the steps of fetching and prefetching access a memory circuit, further comprising the steps of:
assigning a first priority to the first miss in accordance with a state of the memory circuit;
assigning a second priority to the second miss in accordance with the state of the memory circuit in response to the first miss;
determining if the second priority is less important than the first priority; and
wherein the step of halting is not performed if the second priority is less important than the first priority.
7. The method according to claim 1, wherein the first request is received from a lower level cache.
8. A digital system, comprising:
a cache with a plurality of lines, wherein each line is organized as a plurality of segments, the cache having detection circuitry operable to detect if a requested data is present in the cache;
a requesting device connected to the cache to receive requested data from the cache;
a memory circuit connected to the cache;
prefetch circuitry connected to the cache operable to fetch a first segment from the memory circuit for a first line of the cache and further operable to prefetch at least a second segment from the memory circuit for the first line of the cache in response to a first miss detected by the detection circuitry; and
wherein the prefetch circuitry is operable to halt prefetching for the first line of the cache in response to a second miss detected by the detection circuitry.
9. The digital system of claim 8, wherein the prefetch circuitry is operable to prefetch at least a third segment for a second line of the cache in response to the second miss while the prefetch for the first line is halted.
10. The digital system according to claim 8 being a cellular telephone, wherein the requesting device is a processor (CPU), further comprising:
an integrated keyboard connected to the CPU via a keyboard adapter;
a display, connected to the CPU via a display adapter;
radio frequency (RF) circuitry connected to the CPU; and
an aerial connected to the RF circuitry.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A system for buffer clearing for three-dimensional rendering, the system used in a multimedia chip, the multimedia chip being for controlling the three-dimensional rendering and accessing a memory, the memory including a buffer for storing depth data of a plurality of pixels during the three-dimensional rendering, and the multimedia chip including a multimedia related circuit, the system comprising:
a memory interface controller for receiving a conventional command signal from the multimedia related circuit, and for detecting state of the memory; and
a Z clearing controller for receiving X- and Y-coordinates of a pixel that the multimedia related circuit is to draw, and for sending a command signal to the memory interface controller, wherein the Z clearing controller performs Z clearing on the buffer when the memory is in an idle state.
2. A system according to claim 1, wherein the buffer is divided into M segments and the pixels are associated with the M segments.
3. A system according to claim 2, wherein the M segments of the buffer are further associated with M tags, and when Z clearing for one of the M segments is complete, one of the M tags which is associated with the one of the M segment is set to a first value.
4. A system according to claim 3, wherein the first value is one.
5. A system according to claim 3, wherein the first value is zero.
6. A system according to claim 3, wherein the Z clearing controller comprises an index selecting unit.
7. A system according to claim 6, wherein the index selecting unit is used for receiving the X- and Y-coordinates of the pixel that the multimedia related circuit is to draw, and for obtaining one of M indexes by using the X- and Y-coordinates of the pixel that the multimedia related circuit is to draw.
8. A system according to claim 7, wherein the M tags are associated with the M indexes.
9. A system according to claim 3, further comprising a starting address storage unit, wherein when Z clearing for one of the M segments is incomplete, the segment has a portion on which Z clearing is not performed, and a beginning address of the portion is stored in the starting address storage unit and is used as a starting address for Z clearing when Z-clearing is to be performed on the one of the M segments afterwards
10. A system according to claim 1, wherein the command signal is a Z clearing command signal.
11. A system according to claim 1, wherein the memory is inside the multimedia chip.
12. A system according to claim 1, wherein the memory is outside the multimedia chip.
13. A system according to claim 1, wherein the buffer is a Z buffer.
14. A system according to claim 1, wherein when the memory is in the idle state, Z clearing is performed on one of the M segments of the buffer, or a plurality of segments of the M segments of the buffer, or a portion of one of the M segments of the buffer.
15. A system for buffer clearing for three-dimensional rendering, the system used in a multimedia chip, the multimedia chip being for controlling the three-dimensional rendering and accessing a memory, the memory including a Z buffer for storing depth data of a plurality of pixels during the three-dimensional rendering, and the multimedia chip including a multimedia related circuit which includes a three-dimensional engine, the system comprising:
a memory interface controller for receiving a conventional command signal from the multimedia related circuit, and for detecting state of the memory; and
a Z clearing controller for sending a command signal to the memory interface controller, comprising:
a Z clearing tag register having M tags which are associated with M indexes, wherein the Z buffer is divided into M segments which are associated with the M tags;
an index selecting unit for receiving X- and Y-coordinates of a pixel that is to be drawn by the three-dimensional engine and obtaining one of the indexes by using the X- and Y-coordinates of the pixel; and
a starting address storage unit for storing an address of the Z buffer;
wherein the Z clearing controller performs Z clearing on the Z buffer when the memory is in an idle state; when Z clearing for one of the segments is complete, one of the tags associated with the one of the segments is set to a first value; if not, the one of the tags associated with the one of the segments is set to a second value; and when Z clearing for the one of the segments is incomplete, the one of the segments has a portion on which Z clearing is not performed, and a beginning address of the portion is stored in the starting address storage unit.
16. A system according to claim 15, wherein the first value is one and the second value is zero.
17. A system according to claim 15, wherein the first value is zero and the second value is one.
18. A system according to claim 15, wherein the conventional command signal from the multimedia related circuit includes at least one of a write command signal, read command signal, write data signal, and read data signal.
19. A buffer clearing method, for use in three-dimensional rendering, for performing Z clearing on a Z buffer of a memory, the Z buffer being used for storing depth data of a plurality of pixels and being divided into M segments which are associated with M tags, the memory being responsive to a conventional command signal for accessing the memory from a multimedia related circuit, wherein when the multimedia related circuit does not send the conventional command signal to the memory, the memory is in an idle state, the buffer clearing method comprising the steps of:
(a) performing Z clearing on the segment associated with one of the tags which has a first value when the memory is in the idle state;
(b) proceeding to step (c) if the conventional command signal is sent to the memory, and repeating said step (a) if no conventional command signal is sent to the memory;
(c) stopping Z clearing;
(d) setting a value of the tag associated with the segment to a second value if Z clearing for the segment is complete; keeping the value of the tag associated with the segment being the first value if Z clearing for the segment is incomplete; and
(e) repeating from said step (a) to step (e) until Z clearing for the M segments is complete.
20. A buffer clearing method according to claim 19, wherein the first value is zero and the second value is one.
21. A buffer clearing method according to claim 19, wherein the first value is one and the second value is zero.
22. A buffer clearing method according to claim 19, between said step (d) and step (e), further comprising the step of:
(d1) storing a beginning memory address of a portion in the segment on which Z clearing has not performed in a starting address storage unit when Z clearing for the segment is incomplete, wherein the beginning memory address is used as a starting address when Z clearing for the segment is performed afterwards.
23. A buffer clearing method according to claim 19, before said step (a), further comprising the step of:
(a1) performing Z clearing on the Z buffer when an external lock signal is generated, wherein the external lock signal indicates that the Z buffer is to be accessed.
24. A buffer clearing method according to claim 23, wherein performing Z clearing in said step (a1) comprises:
performing Z clearing on the Z buffer completely, or performing Z clearing on a portion of the Z buffer to be accessed, or performing Z clearing on a portion of the Z buffer on which Z clearing has not been performed.
25. A buffer clearing method according to claim 19, before said step (a), further comprising the step of:
(a1) performing Z clearing on the segment completely when an internal lock signal is generated, wherein the internal lock signal indicates that the pixels associated with the segment are to be drawn.
26. A pixel drawing method for use in three-dimensional rendering, for performing drawing for a plurality of pixels P, the pixels P being associated with a Z buffer of a memory, the Z buffer being used for storing the pixels’ depth data during the three-dimensional rendering, the Z buffer being divided into M segments S, each of the pixels P(x, y) being associated with one of the M segments S(i), the M segments being further associated with M tags TAG respectively, wherein when the memory is idle, Z clearing is performed on the Z buffer, and when Z clearing for the segment S(i) is complete, a value of a tag TAG(i) associated with the segment S(i) is set to a first value, the pixel drawing method comprising the steps of:
(a) obtaining the segment S(i) which is associated with the pixel P(x, y) by using the X- and Y-coordinates of the pixel P(x, y), and obtaining the value of the tag TAG(i) associated with the segment S(i);
(b) proceeding to step (c) when the value of the tag TAG(i) is equal to the first value; otherwise, proceeding to step (d);
(c) performing three-dimensional rendering for the pixel P(x, y) and repeating from said step (a) until all of the pixels P are drawn; and
(d) generating an internal lock signal and performing Z clearing on the segment S(i) completely, and repeating from said step (c), wherein the internal lock signal indicates that Z clearing for the segment S(i) associated with the pixel P(x, y) to be drawn is incomplete.
27. A pixel drawing method according to claim 26, wherein the first value is one.
28. A pixel drawing method according to claim 26, wherein the first value is zero.