1. A method for producing a large-area membrane mask upon a multi-layered wafer having a semiconductor layer, a semiconductor carrier layer, a rear side, a center region, and an edge region, the method which comprises:
structuring the semiconductor layer by forming mask openings;
subsequently removing the wafer underneath the mask openings from the rear side by at least one dry-etching step to produce a membrane formed by the structured semiconductor layer and held by a carrying ring; and
covering the wafer in a region of the carrying ring with a masking layer during the at least one dry etching step, thereby causing irregularity of etching conditions between the center region and the edge region of the etched portion of the wafer, and counteracting such irregularity by providing an approximately homogeneous etching removal over an entire area of the wafer to be etched by one of:
for an existing wafer, providing an additional layer construction compensating for the etching irregularity to at least one of a masking region and an open area of the semiconductor carrier layer to be etched;
for an existing wafer, moving a mechanical etching diaphragm in front of the semiconductor carrier layer to expose the edge region to etching attack for a shorter time than the center region; and
during a production of the wafer, providing at least two insulator etching stop layers one on top of the other and separated by an inner semiconductor carrier layer, the inner semiconductor carrier layer being thinner than the semiconductor carrier layer etched in a first partial etching step.
2. The method according to claim 1, wherein the semiconductor carrier layer is a silicon carrier layer, and which further comprises applying a silicon ring, forming one of:
the additional layer construction; and
the masking layer and the additional layer construction,
to the silicon carrier layer in the masking region, the silicon ring having a thickness protecting the silicon carrier layer in the masking region even where the silicon ring is removed by progressive etching.
3. The method according to claim 1, wherein the semiconductor carrier layer is a silicon carrier layer, and which further comprises applying a silicon ring, forming one of the additional layer construction and the masking layer and the additional layer construction to the silicon carrier layer in the masking region, the silicon ring having a thickness protecting the silicon carrier layer in the masking region even where the silicon ring is removed by progressive etching.
4. The method according to claim 1, which further comprises applying a masking pattern, reducing a degree of silicon occupancy of the semiconductor carrier layer, as an additional layer construction to the open area to be etched, so that, after a first dry-etching step, remains of the semiconductor carrier layer corresponding to the masking pattern initially remain.
5. The method according to claim 4, wherein the insulator layer is an insulator stop layer, and which further comprises, removing the remains remaining after the first dry-etching process together with the insulator stop layer in a further etching step by underetching.
6. The method according to claim 4, which further comprises applying the masking pattern by one of:
depositing and subsequently structuring a masking layer; and
attaching a prestructured masking.
7. The method according to claim 6, wherein the prestructure masking is a film structured in a grid shape.
8. The method according to claim 5, which further comprises applying the masking pattern by one of:
depositing and subsequently structuring a masking layer; and
attaching a prestructured masking.
9. The method according to claim 8, wherein the prestructure masking is a film structured in a grid shape.
10. The method according to claim 1, which further comprises producing a gray-scale mask in a transitional masking regionopen area region as an additional layer construction.
11. The method according to claim 1, which further comprises performing etching utilizing a rotating etching diaphragm having a diaphragm opening formed larger in the center region than in the edge region.
12. The method according to claim 1, which further comprises performing etching utilizing a periodically opening and closing iris diaphragm.
13. The method according to claim 1, wherein the wafer has a front side, and which further comprises:
attaching the wafer structured on the front side with the semiconductor layer onto a handle wafer by one of wax and an adhesive film before the dry etching; and
separating the wafer from the handle wafer after the membrane etching.
14. A method for producing a large-area membrane mask upon a wafer having a multi-layer configuration including a semiconductor-insulator-semiconductor carrier structure, a rear sided a center region, and an edge region, the method which comprises:
structuring the semiconductor layer by forming mask openings;
subsequently removing the wafer underneath the mask opening; from the rear side by at least one dry-etching step to produce a membrane formed by the structured semiconductor layer and held by a carrying ring; and
covering the wafer in a region of the carrying ring with a masking layer during the at least one dry etching step, thereby causing irregularity of etching conditions between the center region and the edge region of the etched portion of the wafer, and counteracting such irregularity by providing an approximately homogeneous etching removal over an entire area of the wafer to be etched by one of:
for an existing wafer, providing an additional layer construction compensating for the etching irregularity to at least one of a masking region and an open area of the semiconductor carrier layer to be etched;
for an existing wafer, moving a mechanical etching diaphragm in front of the semiconductor carrier layer to expose the edge region to etching attack for a shorter time than the center region; and
during a production of the wafer, providing at least two insulator etching stop layers one on top of the other and separated by an inner semiconductor carrier layer, the inner semiconductor carrier layer being thinner than the semiconductor carrier layer etched in a first partial etching step.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An uninterruptible power supply device comprising:
a converter converting first ac power from a commercial ac power supply into dc power;
an electric double-layer capacitor storing the dc power;
an inverter converting the dc power from said converter and said electric double-layer capacitor into second ac power;
a rectifier circuit converting said second ac power into dc power; and
a charging circuit supplying output power of said rectifier circuit to said electric double-layer capacitor at a first startup of said inverter, and selectively supplying output power of one of said converter and said rectifier circuit to said electric double-layer capacitor at second and subsequent startups of said inverter.
2. The uninterruptible power supply device according to claim 1, wherein at the second and subsequent startups of said inverter, said charging circuit supplies the output power of said rectifier circuit to said electric double-layer capacitor in a first case determined that a charge level of said electric double-layer capacitor is lower than a predetermined threshold level, and supplies the output power of said converter to said electric double-layer capacitor in a second case determined that the charge level of said electric double-layer capacitor is higher than said predetermined threshold level.
3. The uninterruptible power supply device according to claim 2, wherein said charging circuit determines that the charge level of said electric double-layer capacitor is lower than said predetermined threshold level when a power interruption time of said commercial ac power supply is longer than a predetermined time, and determines that the charge level of said electric double-layer capacitor is higher than said predetermined threshold level when the power interruption time of said commercial ac power supply is shorter than said predetermined time.
4. The uninterruptible power supply device according to claim 2, wherein said charging circuit determines that the charge level of said electric double-layer capacitor is lower than said predetermined threshold level when a voltage across terminals of said electric double-layer capacitor is lower than a predetermined voltage, and determines that the charge level of said electric double-layer capacitor is higher than said predetermined threshold level when the voltage across the terminals of said electric double-layer capacitor is higher than said predetermined voltage.
5. The uninterruptible power supply device according to claim 2, further comprising a switch circuit receiving said first ac power and said second ac power to supply said second ac power to a load in response to termination of said first startup of said inverter, and in a case where a power interruption of said commercial ac power supply occurs, supplying said first ac power to said load in said first case and supplying said second ac power to said load in said second case.
6. The uninterruptible power supply device according to claim 1, further comprising a soft-start circuit increasing an output voltage of said inverter to a target voltage at a first speed at said first startup of said inverter, and increasing the output voltage of said inverter to the target voltage at a second speed faster than said first speed at said second and subsequent startups of said inverter.
7. The uninterruptible power supply device according to claim 6, further comprising a current detection circuit detecting an output current of said rectifier circuit, wherein
said soft-start circuit increases the output voltage of said inverter at one of said first speed and said second speed when a detection value of said current detection circuit is lower than a predetermined threshold current, and temporarily stops increasing the output voltage of said inverter when the detection value of said current detection circuit is higher than said predetermined threshold current.