1. A method comprising:
mirroring a first current corresponding to an input common mode voltage of a first voltage and a second voltage to a third current;
mirroring a second current corresponding to a reference voltage to a fourth current and a fifth current;
mirroring the third current to a sixth current and a seventh current; and
based on the third current, the fourth current, the fifth current, the sixth current, and the seventh current, adjusting the first voltage and the second voltage such that the input common mode voltage changes towards a voltage level of the reference voltage.
2. The method of claim 1, wherein
the first current is provided through a first transistor having the first voltage as an input and a second transistor having the second voltage as an input, and
the second current is provided through a third transistor having the reference voltage as an input.
3. The method of claim 1 further comprising: using a first pair of transistors to adjust the first voltage and the second voltage in a first direction and using a second pair of transistors to adjust the first voltage and the second voltage in a second direction different from the first direction.
4. The method of claim 3 further comprising using a first switch to control the first pair of transistors and using a second switch to control the second pair of transistors.
5. The method of claim 4 further comprising using a first clock generated with reference to a first transition of an input signal to control the first switch and using a second clock generated with reference to a second transition of the input signal to control the second switch.
6. The method of claim 5 further comprising using a first pulse width of the first clock to correspond to a first time to adjust the first voltage and using a second pulse width of the second clock to correspond to a second time to adjust the second voltage.
7. The method of claim 1 further comprising using a first pair of transistors and a second pair of transistors via a feedback connection to the first voltage and the second voltage, to maintain a DC level of the input common mode voltage.
8. The method of claim 1 wherein the sixth current and the fourth current are about equal and the seventh current and the fifth current are about equal.
9. The method of claim 1 further comprising generating an eighth current, a ninth current, a tenth current, and an eleventh current wherein the eighth and the tenth currents are about equal, and the ninth and the eleventh currents are about equal.
10. A circuit comprising:
a first transistor adapted to receive a first voltage;
a second transistor adapted to receive a second voltage, the first transistor and the second transistor adapted to provide a first current;
a third transistor adapted to receive a reference voltage and provide a second current;
a first current mirror adapted to mirror the first current to a third current;
a second current mirror adapted to mirror the second current to a fourth current and a fifth current;
a first pair of output transistors adapted to provide a first feedback path to the first voltage, a first output transistor of the first pair of output transistors adapted to provide the fourth current; and
a second pair of output transistors adapted to provide a second feedback path to the second voltage, a first output transistor of the second pair of output transistors adapted to provide the fifth current.
11. The circuit of claim 10 further comprising a first switch adapted to control the first pair of output transistors and a second switch adapted to control the second pair of output transistors.
12. The circuit of claim 11 wherein when the first pair of output transistors are configured to operate in a first operation mode, the second pair of output transistors are configured to operate in a second operation mode different from the first operation mode.
13. The circuit of claim 10 further comprising a third pair of output transistors that together with the first pair of output transistors are adapted to provide the first feedback path, and a fourth pair of output transistors that together with the second pair of output transistors are adapted to provide the second feedback path.
14. The circuit of claim 13 wherein the third pair of output transistors and fourth pair of output transistors are configured to change a DC level for the first voltage and the second voltage.
15. A circuit comprising:
a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a first pair of output transistors;
a second pair of output transistors;
a third pair of output transistors;
a fourth pair of output transistors
a first switch;
a second switch;
a first current mirror adapted to mirror a first current provided by the first transistor and the second transistor, to the fourth transistor;
a second current mirror adapted to mirror a second current provided by the third transistor to the first pair of output transistors, and, via the first switch, to the second pair of output transistors; and
a third current mirror coupled to the fourth transistor and adapted to mirror a current to the third pair of output transistors, and, via the second switch, to the fourth pair of output transistors;
wherein the first pair of output transistors, the second pair of output transistors, the third pair of output transistors, and the fourth pair of output transistors are adapted to provide feedback paths to inputs of the first transistor and the second transistor.
16. The circuit of claim 15 wherein the first switch is adapted to be controlled by a first clock generated upon a first transition of an input signal and the second switch is adapted to be controlled by a second clock generated upon a second transition of the input signal.
17. The circuit of claim 16 configured to generate one or a combination of pulse widths of the first clock and the second clock that is programmable.
18. The circuit of claim 17 configured to generate the pulse widths of the first clock and the second clock that correspond to respective times to control the second pair of output transistors and to control the fourth pair of output transistors.
19. The circuit of claim 15 wherein the third transistor is adapted to receive a reference voltage used to control a common mode input of the inputs of the first transistor and the second transistor.
20. The circuit of claim 15 wherein when the second pair of transistors are configured to operate in a first mode, the fourth pair of transistors are configured to operate in a second mode different from the first mode
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A non-transitory machine-readable digital memory device comprising:
a series of executable instructions stored in the machine-readable digital memory device, wherein the executable instructions are adapted for operating a reject encoding machine (REM); and wherein the executable instructions include:
first instructions for the REM to identify a mailpiece as being shiny mail;
second instructions for the REM to, in response to identifying the mailpiece as being shiny mail, over-label the mailpiece with at least one non-shiny label;
third instructions for the REM to recognize a destination address of the mailpiece based on a captured digital image;
fourth instructions for the REM to print a barcode corresponding to the destination address onto the non-shiny label; and
fifth instructions for the REM to output the mailpiece for return to downstream processing.
2. The non-transitory machine-readable digital memory device of claim 1, wherein:
the second instructions for the REM to over-label the mailpiece with at least one non-shiny label comprises instructions for the REM to automatically apply a non-shiny label in a POSTNET clear zone on a front side of the mailpiece; and
the fourth instructions for the REM to print a barcode corresponding to the destination address onto the non-shiny label comprises instructions for controlling the REM to print the barcode onto the non-shiny label applied in the POSTNET clear zone.
3. The non-transitory machine-readable digital memory device of claim 1, wherein the second instructions for the REM to over-label the mailpiece with at least one non-shiny label comprises instructions for controlling the REM to apply a non-shiny label to an ID Tag clear zone on the back side of the mailpiece.
4. The non-transitory machine-readable digital memory device of claim 1, wherein the executable instructions further include sixth instructions for the REM to apply a non-shiny label to an ID Tag clear zone on the back side of the mailpiece in response to determining that the third instructions for the REM to recognize a destination address of the mailpiece does not succeed in determining the destination address.
5. A reject encoding machine (REM) including a digital processor configured to execute a series of executable instructions stored in a non-transitory machine-readable digital memory device, wherein the executable instructions include:
instructions for the REM to identify a mailpiece as being shiny mail;
instructions for the REM to, in response to identifying the mailpiece as being shiny mail, over-label the mailpiece with at least one non-shiny label;
instructions for the REM to recognize a destination address of the mailpiece based on a captured digital image;
instructions for the REM to print a barcode corresponding to the destination address onto the non-shiny label; and
instructions for the REM to output the mailpiece for return to downstream processing.
6. The REM of claim 5, wherein the executable instructions further comprise:
instructions for applying a label in the ID Tag clear zone on the mailpiece so as to over-label any pre-existing label in the ID Tag clear zone;
instructions for transferring the mailpiece to a processing machine operating in an Input Sub-System (ISS) mode of operation; and
instructions for printing a barcode in a POSTNET clear zone on the mailpiece that corresponds to the resolved address.
7. The REM of claim 5, wherein the executable instructions further comprise instructions for accessing a Remote Encoding Center (REC) or using Remote Computer Recognition (RCR) to resolve the address.
8. The REM of claim 5, wherein both over-labeling and printing the destination barcode onto the non-shiny label are performed in a single machine.
9. The REM of claim 5, wherein the executable instructions further comprise instructions for transferring the mailpiece to a reject encoding machine (REM) for both over-labeling the mailpiece and printing the destination barcode onto a new label.
10. The REM of claim 9, wherein the executable instructions further comprise instructions for transferring the mailpiece from the REM into a downstream delivery bar code sorter, thereby re-introducing the mailpiece into the automated mail stream rather than being relegated to a manual stream.
11. The REM of claim 5, wherein the destination barcode printed on the label comprises one of an 11-digit delivery point code, a 9-digit zip code, and a 5-digit barcode representing zip code only.
12. The REM of claim 5, wherein the means for over-labeling the mailpiece comprises means for automatically over-labeling the mailpiece with at least one non-shiny label in response to identifying the mailpiece as being shiny mail.
13. A reject encoding machine (REM) including a digital processor configured to execute a series of executable instructions stored in a non-transitory machine-readable digital memory device, the REM further comprising:
means for identifying a mailpiece as being shiny mail;
means for over-labeling the mailpiece with at least one non-shiny label in response to identifying the mailpiece as being shiny mail;
means for recognizing a destination address of the mailpiece based on a captured digital image;
means for printing a barcode corresponding to the recognized destination address onto the non-shiny label; and
means to output the mailpiece for return to downstream processing.
14. The REM of claim 13 wherein:
the means for over-labeling the mailpiece comprises means for automatically applying a non-shiny label in a POSTNET clear zone on a front side of the mailpiece; and
the means for printing a barcode comprises means for printing the barcode onto the non-shiny label applied in the POSTNET clear zone.
15. The REM of claim 13 wherein the means for over-labeling the mailpiece comprises means for applying a non-shiny label to an ID Tag clear zone on the back side of the mailpiece.
16. The REM of claim 13 further comprising means for applying a non-shiny label to an ID Tag clear zone on the back side of the mailpiece in response to determining that the means for recognizing does not succeed in recognizing the destination address.