1. A storage system comprising a first storage controller and a second storage controller,
wherein an actual device of said second storage controller is mapped to a virtual device of said first storage controller; and
wherein said first storage controller comprises a port for transmitting control cylinder information to be written in a control information area of said actual device.
2. The storage system according to claim 1, wherein said second storage controller subjects the user data area of said actual device to 0 padding via physical formatting.
3. The storage system according to claim 1, wherein said first storage controller further comprises a 0 status table for retaining the latest write data regarding the respective blocks in the user data area of said actual device, and returns 0 data to the read access to a prescribed block in the user data area of said actual device when there is no write access to said block in the past, refers to said 0 status table and returns the latest write data when there is write access to said block in the past, and writes the write data in said block in response to the write access to a prescribed block in the user data area of said actual device.
4. A method of formatting a storage system having a first storage controller including a virtual device and a second storage controller including an actual device being mapped to said virtual device, the method comprising the steps of:
transmitting control cylinder information to be written in a control information area of said actual device from said first storage controller to said second storage controller; and
writing said control cylinder information that said second storage controller received from said first storage controller in said control information area of said actual device.
5. The formatting method according to claim 4, wherein said second storage controller subjects the user data area of said actual device to 0 padding via physical formatting.
6. The formatting method according to claim 4, wherein said first storage controller returns 0 data to the read access to a prescribed block in the user data area of said actual device when there is no write access to said block in the past, refers to said 0 status table and returns the latest write data when there is write access to said block in the past, and writes the write data in said block in response to the write access to a prescribed block in the user data area of said actual device.
7. A computer program product having a computer program for causing a storage system having a first storage controller including a virtual device and a second storage controller including an actual device being mapped to said virtual device to format said actual device,
wherein said computer program causes said storage system to execute the steps of:
transmitting control cylinder information to be written in a control information area of said actual device from said first storage controller to said second storage controller; and
writing said control cylinder information that said second storage controller received from said first storage controller in said control information area of said actual device.
8. The computer program product according to claim 7, wherein said computer program causes said second storage controller to execute the step of subjecting the user data area of said actual device to 0 padding via physical formatting.
9. The computer program product according to claim 7, wherein said computer program causes said first storage controller to execute the steps of returning 0 data to the read access to a prescribed block in the user data area of said actual device when there is no write access to said block in the past, referring to said 0 status table and returning the latest write data when there is write access to said block in the past, and writing the write data in said block in response to the write access to a prescribed block in the user data area of said actual device.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A reproduced signal waveform processing apparatus, comprising:
a feedback loop comprising
sampling means for sampling a reproduced signal at an interval of a reproducing clock signal generated at a predetermined oscillation frequency;
a first equalizer for equalizing a digital reproduced signal obtained by the sampling means;
phase frequency control means for detecting a phase error at a frequency between the digital reproduced signal equalized in the first equalizer and the reproducing clock signal, and outputting a control signal in accordance with phase frequency error information between the digital reproduced signal and the reproducing clock signal; and
oscillation means for varying a oscillation frequency in accordance with an instruction from the phase frequency control means,
wherein the feedback loop is a synchronization circuit that functions as a phase locked loop (PLL) for synchronizing frequency phase between the digital reproduced signal and the reproducing clock signal, and
wherein the reproduced signal waveform processing apparatus further comprises a second equalizer connected in series with the first equalizer.
2. The reproduced signal waveform processing apparatus according to claim 1,
wherein the second equalizer means comprises an adaptive equalizer having an automatic equalization function.
3. The reproduced signal waveform processing apparatus according to claim 1,
wherein the first equalizer comprises an IIR filter.
4. The reproduced signal waveform processing apparatus according to claim 1,
wherein the phase frequency control means comprises a FIR filter.
5. The reproduced signal waveform processing apparatus according to claim 1,
wherein an operating clock of the feedback loop is operated at a frequency that is a multiplication of an operating clock of the second equalizer.
6. The reproduced signal waveform processing apparatus according to claim 1, further comprising:
a decimation filter provided between the first and the second equalizers for absorbing a difference in operating clocks of the first and the second equalizers, and
a frequency divider for dividing the reproducing clock signal in the feedback loop and generating a reproducing clock signal that is supplied to the second equalizer.
7. The reproduced signal waveform processing apparatus according to claim 1,
wherein the sampling means is an analogdigital converter.