1. An integrated circuit, comprising:
a first processor;
a plurality of messaging signal registers, wherein the first processor is configured to write a transmit set of messaging signals into the messaging signal registers;
a plurality of GPIO pins;
a GPIO interface configured to receive a first set of signals from the first processor and to transmit a portion of the first set of signals as GPIO signals to a remote processor over the plurality of GPIO pins;
a dedicated transmit pin; and
a finite state machine (FSM) configured to receive a remaining portion of the first set of signals from the GPIO interface and to serially transmit the remaining portion as a transmit set of virtual GPIO signals to the remote processor over the dedicated transmit pin, and wherein the FSM is further configured to retrieve a transmit set of messaging signals from messaging signal register and to serially transmit the transmit set of messaging signals to the remote processor over the dedicated transmit pin.
2. The integrated circuit of claim 1, further comprising:
a dedicated receive pin, wherein the FSM is further configured to serially receive a receive set of virtual GPIO signals from the remote processor over the dedicated receive pin and to provide the receive set of virtual GPIO signals to the GPIO interface.
3. The integrated circuit of claim 2, wherein the GPIO interface is further configured to receive a receive set of GPIO signals from the GPIO pins and to transmit the receive set of GPIO signals to the first processor.
4. The integrated circuit of claim 1, wherein the first processor comprises an application processor.
5. The integrated circuit of claim 1, wherein the first processor comprises a modem processor.
6. The integrated circuit of claim 2, wherein the FSM comprises a parallel-in-serial-out (PISO) shift register and a serial-in-parallel-out (SIPO) shift register.
7. The integrated circuit of claim 2, wherein the FSM is further configured to serially transmit the transmit set of virtual GPIO signals and the transmit set of messaging signals in frames, each frame being demarcated by a start bit and an end bit.
8. The integrated circuit of claim 7, wherein the FSM is further configured to detect a failure of the remote processor by a detection of a failure to receive the end bit for one of the frames.
9. The integrated circuit of claim 3, wherein the FSM if further configured to serially transmit the transmit set of virtual GPIO signals and the transmit set of messaging signals responsive to cycles of an external clock.
10. The integrated circuit of claim 9, wherein the FSM is further configured to serially transmit the transmit sets of signals responsive to first clock edges of the external clock and to serially receive the receive sets responsive to second clock edges of the external clock.
11. The integrated circuit of claim 3, wherein the FSM is further configured to serially transmit the transmit sets of signals as pulse-width-modulated signals.
12. The integrated circuit of claim 11, wherein the FSM includes an oscillator and at least one counter to count oscillations from an oscillator, and wherein the FSM is further configured to determine a pulse width for each pulse-width-modulated signal responsive to a count from the at least one counter.
13. The integrated circuit of claim 12, wherein the oscillator is a ring oscillator.
14. The integrated circuit of claim 11, wherein the FSM is further configured to generate each pulse-width-modulated signal to either have a first pulse width or a second pulse width, wherein the second pulse width is greater than the first pulse width.
15. A method, comprising:
receiving a set of GPIO signals at an GPIO interface from a first processor;
transmitting a portion of the set of GPIO signals through dedicated GPIO pins to a remote processor;
510:
serially transmitting over a dedicated transmit pin a remaining portion of the set of GPIO signals to the remote processor as virtual GPIO signals; and
retrieving messaging signals from messaging signal registers written to by the first processor and serially transmitting the retrieved messaging signals over the dedicated transmit pin to the remote processor.
16. The method of claim 15, further comprising:
serially receiving a receive set of virtual GPIO signals from the remote processor over a dedicated receive pin;
serially receiving a receive set of GPIO signals from the remote processor over the dedicated GPIO pins; and
providing the receive set of virtual GPIO signals and the receive set of GPIO signals to the first processor through the GPIO interface.
17. The method of claim 16, further comprising:
serially receiving a receive set of messaging signals from the remote processor over the dedicated receive pin;
writing the receive set of messaging signals into the messaging signal registers according to addresses for the receive set of messaging signals; and
from the first processor, retrieving the receive set of messaging signals from the messaging signal registers.
18. The method of claim 17, wherein serially transmitting the virtual GPIO signals and the retrieved messaging signals is responsive to cycles of an external clock.
19. The method of claim 17, wherein serially transmitting the virtual GPIO signals and the retrieved messaging signals comprises pulse-width-modulating a transmitted signal over the dedicated transmit pin.
20. An integrated circuit, comprising:
a first processor;
a plurality of messaging signal registers, wherein the first processor is configured to write a transmit set of messaging signals into the messaging signal registers;
a plurality of GPIO pins;
a GPIO interface configured to receive a first set of signals from the processor and to transmit a portion of the first set of signals as GPIO signals to a remote processor over the plurality of GPIO pins;
a dedicated transmit pin; and
a means for receiving a remaining portion of the first set of signals from the GPIO interface and for serially transmitting the remaining portion as a transmit set of virtual GPIO signals to the remote processor over the dedicated transmit pin, and for retrieving a transmit set of messaging signals from messaging signal registers and for serially transmitting the transmit set of messaging signals to the remote processor over the dedicated transmit pin.
21. The integrated circuit of claim 20, wherein the means is configured to serially transmit the transmit sets responsive to cycles of an external clock.
22. The integrated circuit of claim 20, further comprising an oscillator; and wherein the means is configured to serially transmit the transmit sets as pulse-width-modulated signals responsive to counts of oscillations from the oscillator.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A thermally insulating apparatus operatively configured to thermally insulate therein for a period of time, comprising:
an outer shell; and
an internal thermal assembly, positionable within the outer shell, the internal thermal assembly comprising:
a frame sub-assembly cooperating with the outer shell to define a plurality of outer cavities and at least one internal cavity; and
a plurality of insulating members, at least one of the plurality of insulating members being positionable within each of the plurality of outer cavities.