1. A system-on-chip control system, comprising:
a processor for generating a root key for protecting data stored in a memory device connected to the control system;
a root key storage unit for storing the root key; and
a debug port configured to enable an external device to access the control system;
wherein the processor keeps the debug port locked to prevent the external device from accessing the control system if a root key is stored in the storage unit, and unlocks the debug port to enable the external device to access the control system after the root key is erased.
2. The control system as defined in claim 1, wherein the debug port is locked by default when the control system is powered on.
3. The control system as defined in claim 1, wherein the processor erases the root key upon receiving a command to erase the root key from a host device connected to the control system.
4. The control system as defined in claim 1, wherein the root key is generated by entropy collected by the processor.
5. The control system as defined in claim 1, wherein said root key storage unit comprises FLASH memory or a one-time-programmable (OTP) memory.
6. The control system as defined in claim 1, further comprising a debug port interface for enabling the external device to access the control system via the debug port.
7. A method for protecting data stored in a memory device connected to an on-chip control system having a debug port configured to enable an external device to access the control system, the method comprising:
generating a root key for accessing data stored in the memory device;
storing the root key in a root key storage unit; and
keeping the debug port locked to prevent the external device from accessing the data in the memory device through the control system if the root key is stored in the storage unit, and unlocking the debug port to enable the external device to access the control system after the root key is erased.
8. The method as defined in claim 7, wherein the debug port is locked by default when the control system is powered on.
9. The method as defined in claim 7, wherein the root key is erased upon receiving a command to erase the root key from a host device connected to the control system.
10. The method as defined in claim 7, wherein the root key is generated by entropy collected by a processor in the control system.
11. The method as defined in claim 1, wherein the root key storage unit comprises FLASH memory or a one-time-programmable (OTP) memory.
12. A system-on-chip control system of a storage device, comprising:
a host interface configured to be in communication with a host device;
a processor for generating a root key for protecting data stored in a memory device connected to the control system;
a root key storage unit for storing the root key;
a debug port configured to enable an external device to access the control system; and
wherein the processor keeps the debug port locked to prevent the external device from accessing the control system if a root key is stored in the storage unit, and unlocks the debug port to enable the external device to access the control system after the root key is erased.
13. The control system as defined in claim 12, wherein said storage device comprises a disk drive.
14. The storage apparatus as defined in claim 12, wherein said storage device comprises a solid state drive.
15. A storage apparatus, comprising:
at least one storage medium;
a system-on-chip controller including:
a host interface configured to be in communication with a host device;
a processor for generating a root key for protecting data stored in a memory device connected to the control system;
a root key storage unit for storing the root key;
a debug port configured to enable an external device to access the control system; and
wherein the processor keeps the debug port locked to prevent the external device from accessing the control system if a root key is stored in the storage unit, and unlocks the debug port to enable the external device to access the control system after the root key is erased;
a buffer for storing data used by the system-on-chip controller; and
a non-volatile memory for storing programs and tables used by the system-on-chip controller.
16. The storage apparatus as defined in claim 15, wherein said storage medium comprises a disk medium.
17. The storage apparatus as defined in claim 15, wherein said storage medium comprises a solid state storage device.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An apparatus, comprising:
a voltage source to provide a substantially temperature stable output voltage;
a first semiconductor device biased by the substantially temperature stable output voltage to provide a first output current; and
a second semiconductor device biased by the substantially temperature stable output voltage to provide a second output current, the second semiconductor device to couple to the first semiconductor device to provide a reference current approximately equal to a difference between the first and the second output currents.
2. The apparatus of claim 1, wherein the first and the second semiconductor devices are biased by the substantially temperature stable output voltage to operate in a saturation mode.
3. The apparatus of claim 1, wherein the first and the second semiconductor devices are fabricated on a single die.
4. The apparatus of claim 1, further including:
a differencing circuit to couple to the first and the second semiconductor devices.
5. The apparatus of claim 1, further including:
a pair of current mirrors to couple to the first and the second semiconductor devices.
6. The apparatus of claim 5, wherein the first and the second semiconductor devices and the pair of current mirrors are fabricated on a single die.
7. The apparatus of claim 1, wherein a reference magnitude of the reference current is approximately equal to a difference between the second output current and a product of the first output current and a scaling constant.
8. The apparatus of claim 7, further comprising:
a differencing circuit including a first current mirror selected to determine the scaling constant.
9. The integrated circuit of claim 1, wherein the voltage source comprises a band-gap voltage source.
10. An integrated circuit, comprising:
a voltage source to provide a substantially temperature stable output voltage;
a first semiconductor device biased by the substantially temperature stable output voltage to provide a first output current; and
a second semiconductor device biased by the substantially temperature stable output voltage to provide a second output current, the second semiconductor device to couple to the first semiconductor device to provide a reference current approximately equal to a difference between the first and the second output currents; and
an output node in electrical communication with the first and second semiconductor devices to carry the reference current.
11. The integrated circuit of claim 10, wherein the first and the second semiconductor devices are biased by the substantially temperature stable output voltage to operate in a saturation mode.
12. The integrated circuit of claim 10, further including:
a differencing circuit to couple to the first and the second semiconductor devices.
13. The integrated circuit of claim 12, wherein the reference current has a reference magnitude approximately equal to the difference between the second output current and a product of the first output current and a scaling constant determined by a current mirror included in the differencing circuit.
14. The integrated circuit of claim 10, wherein each one of the first and the second semiconductor devices comprise a field effect transistor.
15. The integrated circuit of claim 14, further including:
a pair of current mirrors to couple to the first and the second semiconductor devices, wherein each one of the pair of current mirrors includes a pair of field effect transistors, and wherein the first and the second semiconductor devices and the pair of current mirrors are fabricated on a single die.
16. The integrated circuit of claim 10, wherein the voltage source comprises a band-gap voltage source.
17. A system, comprising:
a cellular telephone including a voltage source to provide a substantially temperature stable output voltage, a first semiconductor device biased by the substantially temperature stable output voltage to provide a first output current, and a second semiconductor device biased by the substantially temperature stable output voltage to provide a second output current, the second semiconductor device to couple to the first semiconductor device to provide a reference current approximately equal to a difference between the first and the second output currents.
18. The system of claim 17, further comprising a differencing circuit to couple to the first and the second semiconductor devices.
19. The system of claim 18, wherein the differencing circuit includes a first current mirror selected to determine a scaling constant.
20. The system of claim 19, wherein the reference current has a reference magnitude approximately equal to the difference between the second output current and a product of the first output current and the scaling constant.