1. A method of manufacturing a semiconductor device having a twin well structure, comprising:
ion-implanting of a first conductivity type impurity in a first region and a second region of a semiconductor substrate, the first and second regions being located adjacent to each other;
forming a first resist pattern to cover the first region of the semiconductor substrate and to expose the second region of the semiconductor substrate;
ion-implanting of a second conductivity type impurity at a higher concentration compared to the first conductivity type impurity in the second region of the semiconductor substrate, with the first resist pattern being used as a mask; and
thermal-diffusing the first conductivity type of impurity and the second conductivity type of impurity.
2. The method according to claim 1, further comprising:
forming a silicon oxide film having a first portion on the first region of the semiconductor substrate and a second portion on the second region of the semiconductor substrate, the second portion having a smaller thickness than that of the first portion;
forming a second resist pattern on the silicon oxide film exposing a part of the first portion and a part of the second portion of the silicon oxide film;
ion-implanting an impurity in a part of the second region of the semiconductor substrate, with the first part of the silicon oxide film and the second resist pattern being used as a mask;
forming a field oxide film by selectively causing the film at the portion of the silicon oxide film exposed from the second resist pattern to grow.
3. The method according to claim 2, wherein the forming of the silicon oxide film comprises:
forming a silicon oxide film on the first region and the second region of the semiconductor substrate before the forming of the first resist pattern; and
forming the second portion of the silicon oxide film, after forming the first resist pattern, by removing an upper portion of the silicon oxide film covering the second region, with the first resist pattern being used as a mask.
4. The method according to claim 2, wherein the forming of the silicon oxide layer comprises:
forming a silicon oxide film on the first region and the second region of the semiconductor substrate before the forming of the first resist pattern;
removing the portion of the silicon oxide film covering the second region, after forming the first resist pattern, with the first resist pattern being used as a mask; and
forming the second portion of the silicon oxide by thermal-oxidizing the second region of the semiconductor substrate by the thermal-diffusion.
5. The method according to claim 1,
wherein a concentration of the second conductivity type impurity is more than double a concentration of the first conductivity type impurity.
6. The method according to claim 1, further comprising performing annealing of the semiconductor substrate in a non-oxidizing atmosphere.
7. The method according to claim 1, further comprising forming an ink supply port passing through the second region of the semiconductor substrate.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for testing a joystick control circuit, wherein said joystick control circuit is connected to a game port that comprises a plurality of pins addressed to a plurality of joystick buttons, comprising steps of:
providing a testing device, latching under an order signal, either shorted circuit or opened circuit in said pins of said game port addressed to said joystick buttons;
connecting said testing device to said game port;
outputting a short circuit signal to said testing device for shorting circuit in said pins addressed to said joystick buttons;
determining whether said joystick control circuit is in a state in accordance with a push-on of said joystick buttons;
outputting an open circuit signal to said testing device for opening circuit in said pins of said game port addressed to said joystick buttons; and
determining whether said joystick control circuit is in a state in accordance with a release of said joystick buttons.
2. The method of claim 1, wherein after outputting said short circuit signal to said testing device, if said joystick control circuit not in a configuration of a push-on of said joystick buttons, said joystick control circuit is evaluated as deficient with respect to a push-on of said joystick buttons.
3. The method of claim 1, wherein after outputting said open circuit signal to said testing device, if said joystick control circuit is not in a configuration of a release of said joystick buttons, said joystick control circuit is evaluated as deficient with respect to a release of said joystick buttons.
4. The method of claim 1, wherein said game port comprises a signal pin through which either said short circuit signal and said open circuit signal can be output to said testing device.
5. A method for testing a joystick control circuit, achieved in a testing device, comprising the steps of testing one of game port pins addressed to a joystick button, wherein said game port pin is connected to said test device, outputting a short circuit signal to a latch device for controlling a switching device of said testing device to be at a short-circuit state, after ascertaining said joystick control circuit which is in a state in accordance with a push-on of said joystick button, outputting an open circuit signal to open the switching device of said testing device.
6. An apparatus for testing a joystick control circuit, wherein said joystick control circuit is connected to a game port to which is connected said apparatus, said game port having a plurality of pins among which is a plurality of pins addressed to a plurality of joystick buttons, comprising:
a connector that has a plurality of pinholes corresponding to said pins of said game port, wherein said pinholes of said connector comprise a signal pinhole and a plurality of pinholes corresponding to said pins of said game port addressed to said joystick buttons;
an electric switch, connected to said pinholes of said connector; and
a latch device, connected to said electric switch and said signal pinhole of said connector, wherein said signal pinhole delivers an order signal to said latch device to command said electric switch to either shorted circuit or opened circuit said pinholes of said connector addressed to said joystick buttons.
7. The apparatus of claim 6, wherein said apparatus further comprises:
a first resistor that simulates a joystick displacement along an X direction;
a second resistor that simulates a joystick displacement along a Y direction;
a third resistor that simulates ajoystick displacement along an X direction; and
a fourth resistor that simulates a joystick displacement along a Y displacement.
8. The apparatus of claim 7, wherein said signal pinhole is connected to one of either said first resistor, said second resistor, said third resistor or said fourth resistor, and serves as an input signal pinhole when said joystick control circuit is tested.
9. The apparatus of claim 8, wherein said pinholes of said connector are:
pinhole 2, connected to said electric switch;
pinhole 3, connected to said first resistor;
pinhole 6, connected to said second resistor;
pinhole 7, connected to said electric switch;
pinhole 10, connected to said electric switch;
pinhole 11, connected to said third resistor;
pinhole 13, connected to said fourth resistor;
pinhole 14, connected to said electric switch;
pinholes 1, 8, and 9 connected to a continuous voltage source; and
pinholes 4 and 5 connected to said electric switch and a ground node.
10. The apparatus of claim 9, wherein said pinholes of said connector that are addressed to said joystick buttons are said pinholes 2, 7, 10, and 14.
11. The apparatus of claim 9, wherein said signal pinhole is said pinhole 3 or 6.
12. The apparatus of claim 6, wherein said electric switch is a transistor.
13. The apparatus of claim 6, wherein said latch device is a flip-flop device.