What is claimed is:
1. A semiconductor device comprising:
a semiconductor substrate;
a first interlayer dielectric film covering the semiconductor substrate;
a second interlayer dielectric film covering the first interlayer dielectric film;
an opening having an upper-layer opening penetrating the second interlayer dielectric film, and a lower-layer opening penetrating the first interlayer dielectric film down to the surface of the semiconductor substrate and being connected to the upper-layer opening, said lower-layer opening being arranged such that diameter of the lower-layer reduces gradually from the upper-layer opening toward the semiconductor substrate; and
a conductive film covering at least the bottom surface of the lower-layer opening and side walls of the lower-layer and upper-layer openings.
2. The device as claimed in claim 1, wherein the upper-layer opening is arranged such that diameter of said upper-layer opening reduces gradually toward the lower-layer opening.
3. The device as claimed in claim 1, wherein diameter of the upper-layer opening is substantially uniform.
4. The device as claimed in 2, said device further comprising:
gate electrodes formed on the semiconductor substrate; and
a passivation insulating film covering the gate electrodes and exposed to a portion of side surfaces of the lower-layer opening.
5. The device as claimed in claim 4, wherein the passivation insulating film is formed under the first interlayer dielectric and covers at least the surface of the semiconductor substrate between the gate electrodes.
6. The device as claimed in claim 5, wherein the lower-layer opening penetrates the passivation insulating film between the gate electrodes down to the surface of the semiconductor substrate.
7. The device as claimed in claim 1, said device further comprising:
a first bit line extending in a first direction;
first and second contacts each connected to said first bit line, said first contact adjacent to said second contact;
a second bit line extending in said first direction and being adjacent to said first bit line; and
a third contact connected to said second bit line, said third contact adjacent to said first contact in said first direction;
wherein distance between said first and third contacts in said first direction is substantially one fourth of distance between said first and second contacts in said first direction.
8. A semiconductor device comprising:
a semiconductor substrate;
a plurality of bit lines formed over said semiconductor substrate arranged in a first direction in that order, each of bit lines extending in a second direction substantially perpendicular to said first direction;
a plurality of bit line contacts connected to the respective bit lines and said semiconductor substrate; and
a plurality of capacitor contacts connected to said semiconductor substrate;
wherein a first bit line contact of said bit line contacts connected to a first bit line of said bit lines and a second bit line contact of said bit line contacts connected to a second bit line of said bit lines are arranged at a line extending in said first direction, said capacitor contacts are arranged at said line.
9. The device as claimed in claim 8, wherein distance between adjacent contacts of adjacent bit lines in said first direction is substantially one fourth of distance between adjacent contacts on said first bit line in said second direction.
10. A method of forming a semiconductor device comprising:
forming a first interlayer insulating film on said semiconductor substrate;
forming a second interlayer insulating film on said first
forming a second interlayer insulating film on said first interlayer insulating film;
forming a first contact hole through said second interlayer insulating film to expose surface of the first interlayer insulating film;
forming a second contact hole through said first interlayer insulating film to expose surface of the semiconductor substrate and being connected to said first contact hole; and
forming a conductive film covering at least the exposed surface of said semiconductor substrate and the side walls of said first and second interlayer insulating films exposed by said first and second contact hole;
wherein said second contact hole is formed into such a shape that diameter of said first contact hole reduces gradually from said second contact hole toward the semiconductor substrate.
11. The method as claimed in claim 10, wherein the second contact hole is arranged such that diameter of said second contact hole reduces gradually toward the first contact hole.
12. The method as claimed in claim 10, wherein diameter of the upper-layer opening is substantially uniform.
13. The method as claimed in claim 11, wherein gate electrodes are formed on the semiconductor substrate, and a passivation insulating film covering the gate electrode is exposed by side surface of the first contact hole.
14. The method as claimed in claim 10, wherein re-deposition depositing on said first interlayer insulating film in case that said second contact hole is greater than re-deposition depositing on said second interlayer insulating film in case that said first contact hole.
15. The method as claimed in claim 14, wherein said re-deposition is controlled by etching gas including Carbon fluoride, Carbon oxide, and Oxygen.
The claims below are in addition to those above.
All refrences to claims which appear below refer to the numbering after this setence.
1. A method of producing an infrared detector comprising:
forming a cadmium mercury telluride (CMT) wafer that includes active device layers having an absorber layer that is sandwiched between two layers with higher x(Cd) that will passivate a diode pn junction where it reaches a surface of a CMT heterostructure;
forming a buffer layer on a substrate, the buffer layer ensuring the absorber layer does not contain dislocations produced by a lattice mismatch between the CMT heterostructure and the substrate;
forming a spacer layer on the buffer layer to space the active device layers from the buffer layer;
forming an etch stop layer on the spacer layer and directly adjacent to the active device layers;
dicing the CMT wafer into an individual CMT die;
bonding the CMT die to an integrated circuit wafer, wherein the active device layers have a uniform thickness;
selectively etching remaining material of the substrate and remaining material of the buffer layer of the CMT die;
forming a loophole focal plane array having a plurality of diodes in CMT monoliths of the active device layers on the integrated circuit wafer; and
dicing the integrated circuit wafer (IC) into an individual IC die following formation of the loophole focal plane array.
2. The method of producing an infra red detector according to claim 1 comprising:
b) bonding the CMT die of the CMT wafer to desired tested sites on readout integrated circuit (ROIC) wafer; and
c) removing the remaining material of the substrate and the remaining material of the buffer layer by selective or non-selective etching to form the CMT monoliths.
3. The method according to claim 2 wherein forming the loophole focal plane array comprises:
forming the array of loophole diodes in the CMT monoliths by ion beam milling through a photo-resist mask and depositing metal through the same mask to form contacts; and
b) dicing said ROIC wafer into individual dies.
4. The method of producing an infra red detector according claim 1, comprising:
a) bonding the CMT die to tested good sites on an ROIC wafer; and
b) removing the remaining material of the substrate and the remaining material of the buffer layer by selective or non-selective etching to form monoliths.
5. The method according to claim 1, wherein forming the loophole focal plane array comprises:
forming the array of loophole diodes in the CMT monoliths by ion beam milling through a photo-resist mask and depositing metal through the same mask to form contacts.
6. The method of producing an infrared detector according to claim 2, wherein forming the loophole focal plane array comprises:
a) forming arrays of pseudo-loophole diodes in the CMT wafer by ion beam milling through a photo-resist mask, and depositing metal through the same photo-resist mask to form contacts;
b) dicing the CMT wafer into individual arrays;
c) bump-bonding said individual arrays to ROICS; and
d) removing the remaining material of the substrate from the arrays by etching.
7. The method of producing an infrared detector according to claim 3, wherein forming the loophole focal plane array comprises:
a) forming arrays of pseudo-loophole diodes in the CMT wafer by ion beam milling through a photo-resist mask, and depositing metal through the same photo-resist mask to form contacts;
b) dicing the CMT wafer into individual arrays;
c) bump-bonding said individual arrays to ROICS; and
d) removing the remaining material of the substrate from the arrays by etching.
8. The method of producing an infrared detector according to claim 1, wherein forming the loophole focal plane array comprises:
a) forming arrays of pseudo-loophole diodes in the CMT wafer by ion beam milling through a photo-resist mask, and depositing metal through the same photo-resist mask to form contacts;
b) dicing the CMT wafer into individual arrays;
c) bump-bonding said individual arrays to ROICS; and
c) removing the remaining material of the substrate from the arrays by etching.