1. A receptacle assembly comprising:
a body portion comprising a front wall, a rear wall, and lateral side walls connecting the front wall and the rear wall, the body portion further comprising an upper edge and a lower edge;
an opening disposed on the rear wall of the body portion; and
a bag liner dispenser positioned near the opening and disposed on an exterior surface of the rear wall, wherein the opening provides access from the bag liner dispenser to an interior space of the body portion.
2. The combination of the receptacle assembly of claim 1 and one or more bag liners.
3. The receptacle assembly of claim 1, wherein the bag liner dispenser is disposed closer to the upper edge of the body portion than the lower edge of the body portion.
4. The receptacle assembly of claim 1, wherein a lower edge of the bag liner dispenser is displaced from the lower edge of the body portion.
5. The receptacle assembly of claim 1, wherein the bag liner dispenser further comprises a dispenser lid.
6. The receptacle assembly of claim 1, further comprising a trim member extending at least partially around the upper edge of the body portion, wherein a thickness of the bag liner dispenser is less than or equal a thickness of a rear portion of the trim member.
7. The receptacle assembly of claim 1, wherein an interior surface of the rear wall is generally planar.
8. The receptacle assembly of claim 1, wherein the opening is generally flush with the rear wall.
9. The receptacle assembly of claim 1, wherein a length of the opening is greater than a height of the opening.
10. The receptacle assembly of claim 1, wherein the opening is displaced from the upper edge of the body portion.
11. The receptacle assembly of claim 1, further comprising an inner body portion disposed within the interior space of the body portion, the inner body portion having an opening that provides access from the bag liner dispenser to an interior space of the inner body portion.
12. The receptacle of claim 1, further comprising a lid portion movably engaged with the body portion, the lid portion connected to the rear wall of the body portion.
13. A method of manufacturing a receptacle assembly comprising:
providing an opening on a rear wall of a body portion, the body portion defining an interior space; and
positioning a bag liner dispenser along an exterior surface of the rear wall and near a periphery of the opening, such that the opening provides access from the bag liner dispenser to the interior space of the body portion.
14. The method of claim 13, further comprising disposing the bag liner dispenser closer to an upper end of the body portion than a lower end of the body portion.
15. The method of claim 13, further comprising connecting a dispenser lid to the bag liner dispenser.
16. The method of claim 13, disposing a trim member at least partially around an upper edge of the body portion, wherein a thickness of the bag liner dispenser is less than or equal a thickness of a rear portion of the trim member.
17. The method of claim 13, wherein an interior surface of the rear wall is generally planar.
18. The method of claim 13, wherein forming the opening comprises forming the opening generally flush with the rear wall.
19. The method of claim 13, wherein forming the opening comprises forming the opening with a length that is greater than a height of the opening.
20. The method of claim 13, wherein forming the opening comprises positioning the opening at a location displaced from an upper edge of the rear wall.
21. The method of claim 13, further comprising inserting an inner body portion into the interior space of the body portion, the inner body portion having an opening that provides access from the bag liner dispenser to an interior space of the inner body portion.
22. The receptacle of claim 13, further comprising connecting a lid portion to the rear wall of the body portion.
23. A method of inserting a liner into a receptacle, the method comprising:
inserting a plurality of bag liners into a bag liner dispenser disposed on an exterior surface of a rear wall of a receptacle, the bag liner dispenser extending around a periphery of an opening disposed on the rear wall of the receptacle; and
pulling a first bag of the plurality of bags through an opening disposed on the rear wall of the body portion into an interior of the receptacle.
The claims below are in addition to those above.
All refrences to claims which appear below refer to the numbering after this setence.
1. An apparatus comprising a data driver circuit, wherein:
the data driver circuit is configured to receive a first data signal and a first clock signal;
the data driver circuit is configured to output a second data signal to be transmitted to a display panel;
the data driver circuit comprises a data driver configured to sample the first data signal according to a second clock signal, obtain the second data signal by analog-converting the first data signal, and output the second data signal;
the data driver circuit comprises a mask signal generator configured to generate a mask signal, wherein the mask signal indicates presence within a predetermined time period measured from when the second data signal begins to change;
the data driver circuit comprises a delay-locked loop (DLL) configured to generate the second clock signal from the first clock signal; and
there is a delay between the first clock signal and the second clock signals, the delay changes due to a phase difference between the first clock signal and the second clock signal, and the changes in the delay due to the phase difference is substantially prevented by the mask signal.
2. The apparatus of claim 1, wherein:
the mask signal is generated at least one of before the second data signal begins to change and at the time the second data signal begins to change; and
the mask signal is maintained for a predetermined period of time after being generated.
3. The apparatus of claim 1, wherein:
a load signal which causes the second data signal to change is applied to the data driver; and
the mask signal generator is configured to generate the mask signal in response to the load signal.
4. The apparatus of claim 3, wherein the data driver comprises:
a sampler configured to sample the first data signal according to the second clock signal;
a latch configured to store an output of the sampler in sequence and output the stored output in parallel in response to the load signal; and
a digital-to-analog converter (DAC) configured to output the second data signal obtained by analog-converting the output of the latch.
5. The apparatus of claim 1, wherein the DLL comprises:
a phase detector configured to obtain the phase difference;
a switch configured to at least one of transmit and block an output of the phase detector;
a low-pass filter (LPF) configured to remove high-frequency components from the output of the switch; and
a delay line configured to derive the second clock signal by delaying the first clock signal, wherein a delay of the delay line changes according to an output of the LPF.
6. The apparatus of claim 5, wherein the switch is configured to transmit a predetermined signal when there is no phase difference to the LPF while blocking the output of the phase detector.
7. The apparatus of claim 1, wherein the DLL comprises:
a phase detector configured to output at least one of the phase difference and a predetermined signal, wherein the predetermined signal indicates that there is no phase difference according to the mask signal;
a low-pass filter (LPF) configured to remove high-frequency components from the output of the phase detector; and
a delay line configured to derive the second clock signal by delaying the first clock signal, wherein a delay of the delay line changes according to an output of the LPF.
8. The apparatus of claim 1, wherein the DLL comprises:
a phase detector configured to obtain the phase difference;
a low-pass filter (LPF) configured to at least one of remove high-frequency components from an output of the phase detector and stop operation according to the mask signal; and
a delay line configured to derive the second clock signal by delaying the first clock signal, wherein a delay of the delay line changes according to an output of the LPF.
9. The apparatus of claim 1, wherein:
the first clock signal is embedded in the first data signal;
the first clock signal has a different signal magnitude than the first data signal; and
a received signal comprises the first clock signal and the first data signal.
10. The apparatus of claim 9, comprising a multi-level detector configured to extract the first clock signal from the received signal and transmit the extracted first clock signal to the DLL.
11. The apparatus of claim 10, wherein the multi-level detector extracts the first data signal and transmits the extracted first data signal to the data driver.
12. The apparatus of claim 9, wherein the first clock signal and the first data signal are transmitted by single-ended signaling using at least one of a single interconnection and by differential signaling using two interconnections.
13. An apparatus comprising a delay-locked loop (DLL) circuit, wherein the DLL comprises:
a DLL configured to generate a second clock signal from a first clock signal, wherein there is a delay between the first clock signal and the second clock signal that changes according to a phase difference between the first clock signal and the second clock signal; and
a mask signal generator configured to transmit a mask signal that prevents the delay from changing according to the phase difference.
14. The apparatus of claim 13, wherein the DLL comprises:
a phase detector configured to obtain the phase difference;
a switch configured to at least one of transmit and block an output of the phase detector according to the mask signal;
a low-pass filter (LPF) configured to remove high-frequency components from the output of the switch; and
a delay line configured to generate the second clock signal by delaying the first clock signal, wherein a delay of the delay line changes according to an output of the LPF.
15. The apparatus of claim 14, wherein the switch is configured to transmit a predetermined signal when there is no phase difference to the LPF while blocking the output of the phase detector.
16. The apparatus of claim 13, comprising:
a phase detector configured to output at least one of the phase difference and a predetermined signal, wherein the predetermined signal indicates that there is no phase difference according to the mask signal;
a low-pass filter (LPF) configured to remove high-frequency components from the output of the phase detector; and
a delay line configured to generate the second clock signal by delaying the first clock signal, wherein a delay of the delay line changes according to an output of the LPF.
17. The apparatus of claim 13, comprising:
a phase detector configured to obtain the phase difference;
a low-pass filter (LPF) configured to at least one of remove high-frequency components from an output of the phase detector and stop operation according to the mask signal; and
a delay line configured to generate the second clock signal by delaying the first clock signal, wherein a delay of the delay line changes according to an output of the LPF.
18. An apparatus comprising a data driver circuit, wherein:
the data driver circuit is configured to receive a first data signal and a first clock signal;
the data driver circuit is configured to output a second data signal to be transmitted to a display panel;
the data driver circuit comprises a delay-locked loop (DLL) configured to generate a second clock signal from the first clock signal;
a delay between the first clock signal and the second clock signal changes according to a phase difference between the first clock signal and the second clock signal;
the delay between the first clock signal and the second clock signal does not change according to the phase difference after the second data signal begins to change; and
the data driver circuit comprises a data driver configured to sample the first data signal in response to the second clock signal, obtain the second data signal by analog-converting the first data signal, and output the second data signal.