1. A method for managing pestware on a protected computer comprising:
tracking activities of a user at the protected computer;
monitoring events at the protected computer;
identifying events that are potentially indicative of pestware;
comparing at least one of the events with at least one of the activities of the user; and
initiating, in response to the comparing indicating the activities of the user are unconnected with the events, a user prompt, wherein the user prompt informs the user about at least one of the events so as to enable the user to make a decision relative to managing the at least one of the events.
2. The method of claim 1, wherein the activities include activities selected from the group consisting of selecting a new homepage, adding a new bookmark and selecting a new search page.
3. The method of claim 1, wherein the tracking activities of a user at the protected computer includes tracking websites visited by the user.
4. The method of claim 1, wherein the tracking activities of a user at the protected computer includes tracking at least one of the user interfaces utilized by the user.
5. The method of claim 4, wherein the at least one of the user interfaces is an options window of a web browser.
6. The method of claim 4, wherein comparing at least one of the events with the activities of the user includes determining whether the at least one of the user interfaces is being utilized when the at least one of the events is detected.
7. The method of claim 3, wherein the at least one of the events is a change to a setting of a browser, wherein the change to the setting includes a pointer to a particular website, and wherein comparing the at least one of the events with the activities of the user includes determining whether the particular website is one of the tracked websites visited by the user.
8. The method of claim 1, wherein the events include events selected from the group consisting of a change in a homepage; an addition of a new bookmark; and change in the search page.
9. A method for reducing false-positive indications of pestware comprising:
monitoring an application of a protected computer;
identifying a change in an application setting, wherein the application setting is utilized by the application;
determining whether the change to the setting was initiated via a process unassociated with the user application; and
informing, in response to the change to the setting being initiated by the process unassociated with the user application, a user of the protected computer about the changed setting.
10. The method of claim 9, wherein the application is a web browser and wherein the application setting is selected from the group consisting of a homepage setting, a bookmark setting and a search page setting.
11. A computer readable medium encoded with processor-executable instructions for managing pestware on a protected computer, the instructions including instructions for:
tracking activities of a user at the protected computer;
monitoring events at the protected computer;
identifying events that are potentially indicative of pestware;
comparing at least one of the events with at least one of the activities of the user; and
initiating, in response to the comparing indicating the activities of the user are unconnected with the events, a user prompt, wherein the user prompt informs the user about at least one of the events so as to enable the user to make a decision relative to managing the at least one of the events.
12. The computer readable medium of claim 11, wherein the activities include activities selected from the group consisting of selecting a new homepage, adding a new bookmark and selecting a new search page.
13. The computer readable medium of claim 11, wherein the instructions for tracking activities of a user at the protected computer include instructions for tracking websites visited by the user.
14. The computer readable medium of claim 11, wherein the instructions for tracking activities of a user at the protected computer includes instructions for tracking at least one of the user interfaces utilized by the user.
15. The computer readable medium of claim 14, wherein the at least one of the user interfaces is an options window of a web browser.
16. The computer readable medium of claim 14, wherein the instructions for comparing at least one of the events with the activities of the user includes instructions for determining whether the at least one of the user interfaces is being utilized when the at least one of the events is detected.
17. The computer readable medium of claim 13, wherein the at least one of the events is a change to a setting of a browser, wherein the change to the setting includes a pointer to a particular website, and wherein the instructions for comparing the at least one of the events with the activities of the user includes instructions for determining whether the particular website is one of the tracked websites visited by the user.
18. The computer readable medium of claim 11, wherein the events include events selected from the group consisting of a change in a homepage; an addition of a new bookmark; and change in the search page.
The claims below are in addition to those above.
All refrences to claims which appear below refer to the numbering after this setence.
What is claimed is:
1. An automatic wiring method for a semiconductor integrated circuit used to form a semiconductor integrated circuit for performing a desired operation by laying out and interconnecting a plurality of macrocells, each implementing a given function, on a semiconductor chip, the method comprising:
(a) a step of arranging a macrocell, in which a plurality of power terminals and a plurality of ground terminals are formed, on the semiconductor chip;
(b) a step of forming a loop line group containing a first power line and a first ground line for supplying power to the macrocell along an outer frame of the macrocell; and
(c) a step of connecting a corresponding one of the power terminals with the first power line that constitutes the loop line group via a second power line, and connecting a corresponding one of the ground terminals with the first ground line that constitutes the loop line group via a second ground line; wherein
the power terminals and the ground terminals are arranged in optimum positions inside the macrocell arranged on the semiconductor chip in the step (a), using the same line layer as the corresponding second power line and second ground line.
2. An automatic wiring method for a semiconductor integrated circuit according to claim 1, wherein the power terminals and the ground terminals are arranged in a plurality of rows along an extending direction of the second power line and the second ground line wired in the step (c), so as to at least partially overlap with the second power line and the second ground line, in the macrocell arranged on the semiconductor chip in the step (a), and only the same type of terminals in the power terminals or the ground terminals of each row are arranged in a straight line along the extending direction.
3. An automatic wiring method for a semiconductor integrated circuit according to claim 2, wherein the second power line and the second ground line are arranged in the step (c) based on information in which at least one of either the power terminals or the ground terminals in corresponding rows is defined.
4. An automatic wiring method for a semiconductor integrated circuit used to form a semiconductor integrated circuit for performing a desired operation by laying out and interconnecting a plurality of macrocells, each implementing a given function, on a semiconductor chip, the method comprising:
(a) a step of arranging a macrocell, in which a plurality of power terminals and a plurality of ground terminals are formed, on the semiconductor chip;
(b) a step of forming a loop line group containing a first power line and a first ground line for supplying power to the macrocell along an outer frame of the macrocell; and
(c) a step of connecting a corresponding one of the power terminals with the first power line that constitutes the loop line group via a second power line, and connecting a corresponding one of the ground terminals with the first ground line that constitutes the loop line group via a second ground line; wherein
a given area, which is set away from the outer frame of the macrocell arranged on the semiconductor chip in the step (a) towards a center of the macrocell, is defined as a wiring limit area in which at least a part of the loop line group can be arranged.
5. An automatic wiring method for a semiconductor integrated circuit according to claim 4, wherein placement of an internal line layer of the macrocell in the same layer as the first power line and the first ground line that constitute the loop line group is prohibited in the wiring limit area.
6. An automatic wiring method for a semiconductor integrated circuit according to claim 1, wherein a part of an internal line layer of the macrocell is formed in the same layer as the power terminals and the ground terminals.
7. An automatic wiring method for a semiconductor integrated circuit according to claim 4, wherein a part of an internal line layer of the macrocell is formed in the same layer as the power terminals and the ground terminals.
8. An automatic wiring method for a semiconductor integrated circuit according to claim 1, wherein the same information that contains positional information about the power terminals and the ground terminals is applied in part of the steps (a), (b), and (c) for macrocell pairs in which arrangement patterns of the power terminals and the ground terminals are in a symmetrical relation with each other.
9. An automatic wiring method for a semiconductor integrated circuit according to claim 4, wherein the same information that contains positional information about the power terminals and the ground terminals is applied in part of the steps (a), (b), and (c) for macrocell pairs in which arrangement patterns of the power terminals and the ground terminals are in a symmetrical relation with each other.
10. An automatic wiring method for a semiconductor integrated circuit according to claim 1, wherein the loop line group contains a chip internal power line located nearest to the outer frame of the macrocell, of chip internal power lines wired at a given interval.
11. An automatic wiring method for a semiconductor integrated circuit according to claim 4, wherein the loop line group contains a chip internal power line located nearest to the outer frame of the macrocell, of chip internal power lines wired at a given interval.
12. An automatic wiring method for a semiconductor integrated circuit according to claim 10, wherein the loop line group is used as a bypass line to connect the chip internal power line with the power terminals and the ground terminals.
13. An automatic wiring method for a semiconductor integrated circuit according to claim 11, wherein the loop line group is used as a bypass line to connect the chip internal power line with the power terminals and the ground terminals.
14. A computer program product, in a computer readable medium, for automatic wiring of a semiconductor integrated circuit used to form a semiconductor integrated circuit for performing a desired operation by laying out and interconnecting a plurality of macrocells, each implementing a given function, on a semiconductor chip, the computer program product comprising:
(a) instruction for arranging a macrocell, in which a plurality of power terminals and a plurality of ground terminals are formed, on the semiconductor chip;
(b) instruction for forming a loop line group containing a first power line and a first ground line for supplying power to the macrocell along an outer frame of the macrocell; and
(c) instruction for connecting a corresponding one of the power terminals with the first power line that constitutes the loop line group via a second power line, and connecting a corresponding one of the ground terminals with the first ground line that constitutes the loop line group via a second ground line; wherein
the power terminals and the ground terminals are arranged in optimum positions inside the macrocell arranged on the semiconductor chip by the instruction (a), using the same line layer as the corresponding second power line and second ground line.
15. A computer program product, in a computer readable medium, for automatic wiring of a semiconductor integrated circuit used to form a semiconductor integrated circuit for performing a desired operation by laying out and interconnecting a plurality of macrocells, each implementing a given function, on a semiconductor chip, the computer program product comprising:
(a) instruction for arranging a macrocell, in which a plurality of power terminals and a plurality of ground terminals are formed, on the semiconductor chip;
(b) instruction for forming a loop line group containing a first power line and a first ground line for supplying power to the macrocell along an outer frame of the macrocell; and
(c) instruction for connecting a corresponding one of the power terminals with the first power line that constitutes the loop line group via a second power line, and connecting a corresponding one of the ground terminals with the first ground line that constitutes the loop line group via a second ground line; wherein
a given area, which is set away from the outer frame of the macrocell arranged on the semiconductor chip by the instruction (a) towards a center of the macrocell, is defined as a wiring limit area in which at least a part of the loop line group can be arranged.
16. A semiconductor integrated circuit for performing a desired operation in which a plurality of interconnected macrocells, each implementing a given function, is laid out on a semiconductor chip, wherein
a plurality of power terminals and a plurality of ground terminals are formed in a macrocell,
a loop line group containing a first power line for supplying power to the macrocell and a first ground line is formed along an outer frame of the macrocell,
a corresponding one of the power terminals is connected with the first power line that constitutes the loop line group via a second power line, and a corresponding one of the ground terminals is connected with the first ground line that constitutes the loop line group via a second ground line, and
the power terminals and the ground terminals are wired using the same line layer as the corresponding second power line and second ground line.
17. A semiconductor integrated circuit according to claim 16, wherein the power terminals and the ground terminals are arranged in a plurality of rows along an extending direction of the second power line and the second ground line, so as to at least partially overlap with the second power line and the second ground line, and only the same type of terminals in the power terminals or the ground terminals are arranged in a straight line along the extending direction.
18. A semiconductor integrated circuit for performing a desired operation in which a plurality of interconnected macrocells, each implementing a given function, is laid out on a semiconductor chip, wherein
a plurality of power terminals and a plurality of ground terminals are formed in a macrocell,
a loop line group containing a first power line for supplying power to the macrocell and a first ground line is formed along an outer frame of the macrocell,
a corresponding one of the power terminals is connected with the first power line that constitutes the loop line group via a second power line, and a corresponding one of the ground terminals is connected with the first ground line that constitutes the loop line group via a second ground line, and
a given area, which is set away from the outer frame of the macrocell towards a center of the macrocell, is defined as a wiring limit area in which at least a part of the loop line group can be arranged.
19. A semiconductor integrated circuit according to claim 18, wherein placement of an internal line layer of the macrocell in the same layer as the first power line and the first ground line that constitute the loop line group is prohibited in the wiring limit area.
20. A semiconductor integrated circuit according to claim 16, wherein a part of an internal line layer of the macrocell is formed in the same layer as the power terminals and the ground terminals.
21. A semiconductor integrated circuit according to claim 18, wherein a part of an internal line layer of the macrocell is formed in the same layer as the power terminals and the ground terminals.
22. A semiconductor integrated circuit according to claim 16, wherein the loop line group contains a chip internal power line located nearest to the outer frame of the macrocell, of chip internal power lines wired at a given interval.
23. A semiconductor integrated circuit according to claim 18, wherein the loop line group contains a chip internal power line located nearest to the outer frame of the macrocell, of chip internal power lines wired at a given interval.
24. A semiconductor integrated circuit according to claim 22, wherein the loop line group is used as a bypass line to connect the chip internal power line with the power terminals and the ground terminals.
25. A semiconductor integrated circuit according to claim 23, wherein the loop line group is used as a bypass line to connect the chip internal power line with the power terminals and the ground terminals.
26. An automatic wiring method for performing a wiring layout using a multilayer line in an electronic computer, comprising:
(a) a step of wiring a first constant potential line for transmitting a constant potential as a power source in an area outside of a macrocell;
(b) a step of acquiring position information for a terminal disposed in the macrocell from a terminal library; and
(c) a step of wiring a second constant potential line for connecting the first constant potential line and the terminal in the same line layer as the terminal based on the acquired position information.
27. An automatic wiring method according to claim 26, wherein the first constant potential line is a ground line.
28. An automatic wiring method according to claim 26, wherein position information for a row of terminals composed of a plurality of terminals lined up in one direction is acquired from the terminal library in the step (b), and the row of terminals and the first constant potential line are connected and the first constant potential line is wired so as to overlap with the row of terminals in the step (c).
29. An automatic wiring method according to claim 28, wherein the position information for the row of terminals is expressed as position information for one terminal contained in the row of terminals.
30. An automatic wiring method according to claim 26, wherein a plurality of terminals arranged in a matrix to which the constant potential is supplied is formed in the macrocell, and the terminal library comprises position information for each of the terminals contained in one terminal line of the matrix, and position information for each of the terminals contained in one terminal row.
31. A semiconductor integrated circuit comprising:
a macrocell;
a first constant potential line formed in an area outside the macrocell for transmitting a constant potential as a power source;
a terminal disposed inside the macrocell and to which the constant potential is supplied; and
a second constant potential line formed in the same line layer as the terminal, for connecting the first constant potential line with the terminal.
32. A computer program product, in a computer readable medium, for automatic wiring to perform a wiring layout using a multilayer line in an electronic computer, comprising:
instruction for wiring a first constant potential line for transmitting a constant potential as a power source in an area outside of a macrocell;
instruction for acquiring position information for a terminal disposed in the macrocell from a terminal library; and
instruction for wiring a second constant potential line for connecting the first constant potential line and the terminal in the same line layer as the terminal based on the acquired position information.
33. An automatic wiring method for performing a wiring layout in an electronic computer, comprising:
a step of acquiring a macrocell from a library and arranging the macrocell;
a step of wiring a loop line group for transmitting a power supply voltage in a vicinity and in a predefined area of the macrocell;
a step of acquiring position information for a terminal disposed in the macrocell from a library; and
a step of wiring a connection line for connecting the loop line group and the terminal based on the acquired position information.
34. A computer program product, in a computer readable medium, for automatic wiring to perform a wiring layout in an electronic computer, comprising:
instruction for acquiring a macrocell from a library and arranging the macrocell;
instruction for wiring a loop line group for transmitting a power supply voltage in a vicinity and in a predefined area of the macrocell;
instruction for acquiring position information for a terminal disposed in the macrocell from a library; and
instruction for wiring a connection line for connecting the loop line group and the terminal based on the acquired position information.
35. A semiconductor integrated circuit comprising:
a macrocell in which a plurality of terminals is formed;
a loop line group for transmitting power supply voltage in a vicinity and in a predefined area of the macrocell; and
a connection line for connecting the loop line group and the plurality of terminals.
36. A semiconductor integrated circuit according to claim 35, wherein the connection line and the plurality of terminals are formed in the same line layer.